epptop.tan.qmsg

在altera fpga中实现epp模式的并口通信程序

{ "Info" "ITDB_TH_RESULT" "EPP2SRAM:M0\|epp_datain\[3\] EPPDATA\[3\] CLK -3.324 ns register " "Info: th for register \"EPP2SRAM:M0\|epp_datain\[3\]\" (data pin = \"EPPDATA\[3\]\", clock pin = \"CLK\") is -3.324 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.427 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 3.427 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.083 ns) 1.083 ns CLK 1 CLK PIN_A16 1 " "Info: 1: + IC(0.000 ns) + CELL(1.083 ns) = 1.083 ns; Loc. = PIN_A16; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "EPPTOP.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPPTOP.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.474 ns) + CELL(0.000 ns) 1.557 ns CLK~clkctrl 2 COMB CLKCTRL_G15 106 " "Info: 2: + IC(0.474 ns) + CELL(0.000 ns) = 1.557 ns; Loc. = CLKCTRL_G15; Fanout = 106; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.474 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "EPPTOP.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPPTOP.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.042 ns) + CELL(0.828 ns) 3.427 ns EPP2SRAM:M0\|epp_datain\[3\] 3 REG LCFF_X48_Y34_N19 1 " "Info: 3: + IC(1.042 ns) + CELL(0.828 ns) = 3.427 ns; Loc. = LCFF_X48_Y34_N19; Fanout = 1; REG Node = 'EPP2SRAM:M0\|epp_datain\[3\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.870 ns" { CLK~clkctrl EPP2SRAM:M0|epp_datain[3] } "NODE_NAME" } } { "EPP2SRAM.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPP2SRAM.v" 133 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.911 ns ( 55.76 % ) " "Info: Total cell delay = 1.911 ns ( 55.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.516 ns ( 44.24 % ) " "Info: Total interconnect delay = 1.516 ns ( 44.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.427 ns" { CLK CLK~clkctrl EPP2SRAM:M0|epp_datain[3] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.427 ns" { CLK CLK~combout CLK~clkctrl EPP2SRAM:M0|epp_datain[3] } { 0.000ns 0.000ns 0.474ns 1.042ns } { 0.000ns 1.083ns 0.000ns 0.828ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.200 ns + " "Info: + Micro hold delay of destination is 0.200 ns" {  } { { "EPP2SRAM.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPP2SRAM.v" 133 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.951 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.951 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns EPPDATA\[3\] 1 PIN PIN_C11 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_C11; Fanout = 1; PIN Node = 'EPPDATA\[3\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { EPPDATA[3] } "NODE_NAME" } } { "EPPTOP.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPPTOP.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.134 ns) 1.134 ns EPPDATA\[3\]~4 2 COMB IOC_X51_Y37_N0 1 " "Info: 2: + IC(0.000 ns) + CELL(1.134 ns) = 1.134 ns; Loc. = IOC_X51_Y37_N0; Fanout = 1; COMB Node = 'EPPDATA\[3\]~4'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.134 ns" { EPPDATA[3] EPPDATA[3]~4 } "NODE_NAME" } } { "EPPTOP.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPPTOP.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.308 ns) + CELL(0.302 ns) 6.744 ns EPP2SRAM:M0\|epp_datain\[7\]~550 3 COMB LCCOMB_X48_Y34_N18 1 " "Info: 3: + IC(5.308 ns) + CELL(0.302 ns) = 6.744 ns; Loc. = LCCOMB_X48_Y34_N18; Fanout = 1; COMB Node = 'EPP2SRAM:M0\|epp_datain\[7\]~550'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.610 ns" { EPPDATA[3]~4 EPP2SRAM:M0|epp_datain[7]~550 } "NODE_NAME" } } { "EPP2SRAM.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPP2SRAM.v" 133 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.207 ns) 6.951 ns EPP2SRAM:M0\|epp_datain\[3\] 4 REG LCFF_X48_Y34_N19 1 " "Info: 4: + IC(0.000 ns) + CELL(0.207 ns) = 6.951 ns; Loc. = LCFF_X48_Y34_N19; Fanout = 1; REG Node = 'EPP2SRAM:M0\|epp_datain\[3\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.207 ns" { EPP2SRAM:M0|epp_datain[7]~550 EPP2SRAM:M0|epp_datain[3] } "NODE_NAME" } } { "EPP2SRAM.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPP2SRAM.v" 133 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.643 ns ( 23.64 % ) " "Info: Total cell delay = 1.643 ns ( 23.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.308 ns ( 76.36 % ) " "Info: Total interconnect delay = 5.308 ns ( 76.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.951 ns" { EPPDATA[3] EPPDATA[3]~4 EPP2SRAM:M0|epp_datain[7]~550 EPP2SRAM:M0|epp_datain[3] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.951 ns" { EPPDATA[3] EPPDATA[3]~4 EPP2SRAM:M0|epp_datain[7]~550 EPP2SRAM:M0|epp_datain[3] } { 0.000ns 0.000ns 5.308ns 0.000ns } { 0.000ns 1.134ns 0.302ns 0.207ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.427 ns" { CLK CLK~clkctrl EPP2SRAM:M0|epp_datain[3] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.427 ns" { CLK CLK~combout CLK~clkctrl EPP2SRAM:M0|epp_datain[3] } { 0.000ns 0.000ns 0.474ns 1.042ns } { 0.000ns 1.083ns 0.000ns 0.828ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.951 ns" { EPPDATA[3] EPPDATA[3]~4 EPP2SRAM:M0|epp_datain[7]~550 EPP2SRAM:M0|epp_datain[3] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.951 ns" { EPPDATA[3] EPPDATA[3]~4 EPP2SRAM:M0|epp_datain[7]~550 EPP2SRAM:M0|epp_datain[3] } { 0.000ns 0.000ns 5.308ns 0.000ns } { 0.000ns 1.134ns 0.302ns 0.207ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "111 " "Info: Allocated 111 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 30 21:44:41 2008 " "Info: Processing ended: Tue Dec 30 21:44:41 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}