epptop.tan.qmsg

在altera fpga中实现epp模式的并口通信程序

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register EPP2SRAM:M0\|sram_raddr\[2\] register ram_dp_ar_aw:m1\|data_0_out\[0\] 222.87 MHz 4.487 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 222.87 MHz between source register \"EPP2SRAM:M0\|sram_raddr\[2\]\" and destination register \"ram_dp_ar_aw:m1\|data_0_out\[0\]\" (period= 4.487 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.239 ns + Longest register register " "Info: + Longest register to register delay is 4.239 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns EPP2SRAM:M0\|sram_raddr\[2\] 1 REG LCFF_X49_Y31_N21 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X49_Y31_N21; Fanout = 2; REG Node = 'EPP2SRAM:M0\|sram_raddr\[2\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { EPP2SRAM:M0|sram_raddr[2] } "NODE_NAME" } } { "EPP2SRAM.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPP2SRAM.v" 133 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.326 ns) + CELL(0.306 ns) 0.632 ns EPP2SRAM:M0\|SRAM_ADDR\[2\]~162 2 COMB LCCOMB_X49_Y31_N28 17 " "Info: 2: + IC(0.326 ns) + CELL(0.306 ns) = 0.632 ns; Loc. = LCCOMB_X49_Y31_N28; Fanout = 17; COMB Node = 'EPP2SRAM:M0\|SRAM_ADDR\[2\]~162'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.632 ns" { EPP2SRAM:M0|sram_raddr[2] EPP2SRAM:M0|SRAM_ADDR[2]~162 } "NODE_NAME" } } { "EPP2SRAM.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPP2SRAM.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.907 ns) + CELL(0.306 ns) 1.845 ns ram_dp_ar_aw:m1\|data_0_out\[0\]~1231 3 COMB LCCOMB_X48_Y33_N4 9 " "Info: 3: + IC(0.907 ns) + CELL(0.306 ns) = 1.845 ns; Loc. = LCCOMB_X48_Y33_N4; Fanout = 9; COMB Node = 'ram_dp_ar_aw:m1\|data_0_out\[0\]~1231'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.213 ns" { EPP2SRAM:M0|SRAM_ADDR[2]~162 ram_dp_ar_aw:m1|data_0_out[0]~1231 } "NODE_NAME" } } { "ram_dp_ar_aw.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/ram_dp_ar_aw.v" 97 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.918 ns) + CELL(0.464 ns) 3.227 ns ram_dp_ar_aw:m1\|data_0_out~1254 4 COMB LCCOMB_X49_Y31_N22 1 " "Info: 4: + IC(0.918 ns) + CELL(0.464 ns) = 3.227 ns; Loc. = LCCOMB_X49_Y31_N22; Fanout = 1; COMB Node = 'ram_dp_ar_aw:m1\|data_0_out~1254'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.382 ns" { ram_dp_ar_aw:m1|data_0_out[0]~1231 ram_dp_ar_aw:m1|data_0_out~1254 } "NODE_NAME" } } { "ram_dp_ar_aw.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/ram_dp_ar_aw.v" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.341 ns) + CELL(0.464 ns) 4.032 ns ram_dp_ar_aw:m1\|data_0_out~1255 5 COMB LCCOMB_X49_Y31_N30 1 " "Info: 5: + IC(0.341 ns) + CELL(0.464 ns) = 4.032 ns; Loc. = LCCOMB_X49_Y31_N30; Fanout = 1; COMB Node = 'ram_dp_ar_aw:m1\|data_0_out~1255'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.805 ns" { ram_dp_ar_aw:m1|data_0_out~1254 ram_dp_ar_aw:m1|data_0_out~1255 } "NODE_NAME" } } { "ram_dp_ar_aw.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/ram_dp_ar_aw.v" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.207 ns) 4.239 ns ram_dp_ar_aw:m1\|data_0_out\[0\] 6 REG LCFF_X49_Y31_N31 1 " "Info: 6: + IC(0.000 ns) + CELL(0.207 ns) = 4.239 ns; Loc. = LCFF_X49_Y31_N31; Fanout = 1; REG Node = 'ram_dp_ar_aw:m1\|data_0_out\[0\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.207 ns" { ram_dp_ar_aw:m1|data_0_out~1255 ram_dp_ar_aw:m1|data_0_out[0] } "NODE_NAME" } } { "ram_dp_ar_aw.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/ram_dp_ar_aw.v" 97 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.747 ns ( 41.21 % ) " "Info: Total cell delay = 1.747 ns ( 41.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.492 ns ( 58.79 % ) " "Info: Total interconnect delay = 2.492 ns ( 58.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.239 ns" { EPP2SRAM:M0|sram_raddr[2] EPP2SRAM:M0|SRAM_ADDR[2]~162 ram_dp_ar_aw:m1|data_0_out[0]~1231 ram_dp_ar_aw:m1|data_0_out~1254 ram_dp_ar_aw:m1|data_0_out~1255 ram_dp_ar_aw:m1|data_0_out[0] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.239 ns" { EPP2SRAM:M0|sram_raddr[2] EPP2SRAM:M0|SRAM_ADDR[2]~162 ram_dp_ar_aw:m1|data_0_out[0]~1231 ram_dp_ar_aw:m1|data_0_out~1254 ram_dp_ar_aw:m1|data_0_out~1255 ram_dp_ar_aw:m1|data_0_out[0] } { 0.000ns 0.326ns 0.907ns 0.918ns 0.341ns 0.000ns } { 0.000ns 0.306ns 0.306ns 0.464ns 0.464ns 0.207ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.416 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 3.416 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.083 ns) 1.083 ns CLK 1 CLK PIN_A16 1 " "Info: 1: + IC(0.000 ns) + CELL(1.083 ns) = 1.083 ns; Loc. = PIN_A16; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "EPPTOP.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPPTOP.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.474 ns) + CELL(0.000 ns) 1.557 ns CLK~clkctrl 2 COMB CLKCTRL_G15 106 " "Info: 2: + IC(0.474 ns) + CELL(0.000 ns) = 1.557 ns; Loc. = CLKCTRL_G15; Fanout = 106; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.474 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "EPPTOP.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPPTOP.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.828 ns) 3.416 ns ram_dp_ar_aw:m1\|data_0_out\[0\] 3 REG LCFF_X49_Y31_N31 1 " "Info: 3: + IC(1.031 ns) + CELL(0.828 ns) = 3.416 ns; Loc. = LCFF_X49_Y31_N31; Fanout = 1; REG Node = 'ram_dp_ar_aw:m1\|data_0_out\[0\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.859 ns" { CLK~clkctrl ram_dp_ar_aw:m1|data_0_out[0] } "NODE_NAME" } } { "ram_dp_ar_aw.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/ram_dp_ar_aw.v" 97 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.911 ns ( 55.94 % ) " "Info: Total cell delay = 1.911 ns ( 55.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.505 ns ( 44.06 % ) " "Info: Total interconnect delay = 1.505 ns ( 44.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.416 ns" { CLK CLK~clkctrl ram_dp_ar_aw:m1|data_0_out[0] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.416 ns" { CLK CLK~combout CLK~clkctrl ram_dp_ar_aw:m1|data_0_out[0] } { 0.000ns 0.000ns 0.474ns 1.031ns } { 0.000ns 1.083ns 0.000ns 0.828ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.416 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 3.416 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.083 ns) 1.083 ns CLK 1 CLK PIN_A16 1 " "Info: 1: + IC(0.000 ns) + CELL(1.083 ns) = 1.083 ns; Loc. = PIN_A16; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "EPPTOP.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPPTOP.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.474 ns) + CELL(0.000 ns) 1.557 ns CLK~clkctrl 2 COMB CLKCTRL_G15 106 " "Info: 2: + IC(0.474 ns) + CELL(0.000 ns) = 1.557 ns; Loc. = CLKCTRL_G15; Fanout = 106; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.474 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "EPPTOP.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPPTOP.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.828 ns) 3.416 ns EPP2SRAM:M0\|sram_raddr\[2\] 3 REG LCFF_X49_Y31_N21 2 " "Info: 3: + IC(1.031 ns) + CELL(0.828 ns) = 3.416 ns; Loc. = LCFF_X49_Y31_N21; Fanout = 2; REG Node = 'EPP2SRAM:M0\|sram_raddr\[2\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.859 ns" { CLK~clkctrl EPP2SRAM:M0|sram_raddr[2] } "NODE_NAME" } } { "EPP2SRAM.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPP2SRAM.v" 133 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.911 ns ( 55.94 % ) " "Info: Total cell delay = 1.911 ns ( 55.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.505 ns ( 44.06 % ) " "Info: Total interconnect delay = 1.505 ns ( 44.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.416 ns" { CLK CLK~clkctrl EPP2SRAM:M0|sram_raddr[2] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.416 ns" { CLK CLK~combout CLK~clkctrl EPP2SRAM:M0|sram_raddr[2] } { 0.000ns 0.000ns 0.474ns 1.031ns } { 0.000ns 1.083ns 0.000ns 0.828ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.416 ns" { CLK CLK~clkctrl ram_dp_ar_aw:m1|data_0_out[0] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.416 ns" { CLK CLK~combout CLK~clkctrl ram_dp_ar_aw:m1|data_0_out[0] } { 0.000ns 0.000ns 0.474ns 1.031ns } { 0.000ns 1.083ns 0.000ns 0.828ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.416 ns" { CLK CLK~clkctrl EPP2SRAM:M0|sram_raddr[2] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.416 ns" { CLK CLK~combout CLK~clkctrl EPP2SRAM:M0|sram_raddr[2] } { 0.000ns 0.000ns 0.474ns 1.031ns } { 0.000ns 1.083ns 0.000ns 0.828ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.127 ns + " "Info: + Micro clock to output delay of source is 0.127 ns" {  } { { "EPP2SRAM.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPP2SRAM.v" 133 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.121 ns + " "Info: + Micro setup delay of destination is 0.121 ns" {  } { { "ram_dp_ar_aw.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/ram_dp_ar_aw.v" 97 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.239 ns" { EPP2SRAM:M0|sram_raddr[2] EPP2SRAM:M0|SRAM_ADDR[2]~162 ram_dp_ar_aw:m1|data_0_out[0]~1231 ram_dp_ar_aw:m1|data_0_out~1254 ram_dp_ar_aw:m1|data_0_out~1255 ram_dp_ar_aw:m1|data_0_out[0] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.239 ns" { EPP2SRAM:M0|sram_raddr[2] EPP2SRAM:M0|SRAM_ADDR[2]~162 ram_dp_ar_aw:m1|data_0_out[0]~1231 ram_dp_ar_aw:m1|data_0_out~1254 ram_dp_ar_aw:m1|data_0_out~1255 ram_dp_ar_aw:m1|data_0_out[0] } { 0.000ns 0.326ns 0.907ns 0.918ns 0.341ns 0.000ns } { 0.000ns 0.306ns 0.306ns 0.464ns 0.464ns 0.207ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.416 ns" { CLK CLK~clkctrl ram_dp_ar_aw:m1|data_0_out[0] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.416 ns" { CLK CLK~combout CLK~clkctrl ram_dp_ar_aw:m1|data_0_out[0] } { 0.000ns 0.000ns 0.474ns 1.031ns } { 0.000ns 1.083ns 0.000ns 0.828ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.416 ns" { CLK CLK~clkctrl EPP2SRAM:M0|sram_raddr[2] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.416 ns" { CLK CLK~combout CLK~clkctrl EPP2SRAM:M0|sram_raddr[2] } { 0.000ns 0.000ns 0.474ns 1.031ns } { 0.000ns 1.083ns 0.000ns 0.828ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "ram_dp_ar_aw:m1\|mem\[2\]\[2\] SRAMADDR\[2\] CLK 10.349 ns register " "Info: tsu for register \"ram_dp_ar_aw:m1\|mem\[2\]\[2\]\" (data pin = \"SRAMADDR\[2\]\", clock pin = \"CLK\") is 10.349 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.703 ns + Longest pin register " "Info: + Longest pin to register delay is 13.703 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.134 ns) 1.134 ns SRAMADDR\[2\] 1 PIN PIN_E11 19 " "Info: 1: + IC(0.000 ns) + CELL(1.134 ns) = 1.134 ns; Loc. = PIN_E11; Fanout = 19; PIN Node = 'SRAMADDR\[2\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAMADDR[2] } "NODE_NAME" } } { "EPPTOP.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPPTOP.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.021 ns) + CELL(0.464 ns) 7.619 ns ram_dp_ar_aw:m1\|mem\[1\]\[2\]~3355 2 COMB LCCOMB_X48_Y32_N0 3 " "Info: 2: + IC(6.021 ns) + CELL(0.464 ns) = 7.619 ns; Loc. = LCCOMB_X48_Y32_N0; Fanout = 3; COMB Node = 'ram_dp_ar_aw:m1\|mem\[1\]\[2\]~3355'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.485 ns" { SRAMADDR[2] ram_dp_ar_aw:m1|mem[1][2]~3355 } "NODE_NAME" } } { "ram_dp_ar_aw.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/ram_dp_ar_aw.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.907 ns) + CELL(0.302 ns) 8.828 ns ram_dp_ar_aw:m1\|mem\[0\]\[6\]~3359 3 COMB LCCOMB_X47_Y33_N0 2 " "Info: 3: + IC(0.907 ns) + CELL(0.302 ns) = 8.828 ns; Loc. = LCCOMB_X47_Y33_N0; Fanout = 2; COMB Node = 'ram_dp_ar_aw:m1\|mem\[0\]\[6\]~3359'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.209 ns" { ram_dp_ar_aw:m1|mem[1][2]~3355 ram_dp_ar_aw:m1|mem[0][6]~3359 } "NODE_NAME" } } { "ram_dp_ar_aw.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/ram_dp_ar_aw.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.327 ns) + CELL(0.507 ns) 11.662 ns ram_dp_ar_aw:m1\|mem\[2\]\[4\]~3373 4 COMB LCCOMB_X47_Y33_N28 8 " "Info: 4: + IC(2.327 ns) + CELL(0.507 ns) = 11.662 ns; Loc. = LCCOMB_X47_Y33_N28; Fanout = 8; COMB Node = 'ram_dp_ar_aw:m1\|mem\[2\]\[4\]~3373'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.834 ns" { ram_dp_ar_aw:m1|mem[0][6]~3359 ram_dp_ar_aw:m1|mem[2][4]~3373 } "NODE_NAME" } } { "ram_dp_ar_aw.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/ram_dp_ar_aw.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.041 ns) + CELL(1.000 ns) 13.703 ns ram_dp_ar_aw:m1\|mem\[2\]\[2\] 5 REG LCFF_X46_Y31_N9 2 " "Info: 5: + IC(1.041 ns) + CELL(1.000 ns) = 13.703 ns; Loc. = LCFF_X46_Y31_N9; Fanout = 2; REG Node = 'ram_dp_ar_aw:m1\|mem\[2\]\[2\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.041 ns" { ram_dp_ar_aw:m1|mem[2][4]~3373 ram_dp_ar_aw:m1|mem[2][2] } "NODE_NAME" } } { "ram_dp_ar_aw.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/ram_dp_ar_aw.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.407 ns ( 24.86 % ) " "Info: Total cell delay = 3.407 ns ( 24.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.296 ns ( 75.14 % ) " "Info: Total interconnect delay = 10.296 ns ( 75.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "13.703 ns" { SRAMADDR[2] ram_dp_ar_aw:m1|mem[1][2]~3355 ram_dp_ar_aw:m1|mem[0][6]~3359 ram_dp_ar_aw:m1|mem[2][4]~3373 ram_dp_ar_aw:m1|mem[2][2] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "13.703 ns" { SRAMADDR[2] SRAMADDR[2]~combout ram_dp_ar_aw:m1|mem[1][2]~3355 ram_dp_ar_aw:m1|mem[0][6]~3359 ram_dp_ar_aw:m1|mem[2][4]~3373 ram_dp_ar_aw:m1|mem[2][2] } { 0.000ns 0.000ns 6.021ns 0.907ns 2.327ns 1.041ns } { 0.000ns 1.134ns 0.464ns 0.302ns 0.507ns 1.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.121 ns + " "Info: + Micro setup delay of destination is 0.121 ns" {  } { { "ram_dp_ar_aw.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/ram_dp_ar_aw.v" 45 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 3.475 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 3.475 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.083 ns) 1.083 ns CLK 1 CLK PIN_A16 1 " "Info: 1: + IC(0.000 ns) + CELL(1.083 ns) = 1.083 ns; Loc. = PIN_A16; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "EPPTOP.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPPTOP.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.474 ns) + CELL(0.000 ns) 1.557 ns CLK~clkctrl 2 COMB CLKCTRL_G15 106 " "Info: 2: + IC(0.474 ns) + CELL(0.000 ns) = 1.557 ns; Loc. = CLKCTRL_G15; Fanout = 106; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.474 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "EPPTOP.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPPTOP.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.090 ns) + CELL(0.828 ns) 3.475 ns ram_dp_ar_aw:m1\|mem\[2\]\[2\] 3 REG LCFF_X46_Y31_N9 2 " "Info: 3: + IC(1.090 ns) + CELL(0.828 ns) = 3.475 ns; Loc. = LCFF_X46_Y31_N9; Fanout = 2; REG Node = 'ram_dp_ar_aw:m1\|mem\[2\]\[2\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.918 ns" { CLK~clkctrl ram_dp_ar_aw:m1|mem[2][2] } "NODE_NAME" } } { "ram_dp_ar_aw.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/ram_dp_ar_aw.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.911 ns ( 54.99 % ) " "Info: Total cell delay = 1.911 ns ( 54.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.564 ns ( 45.01 % ) " "Info: Total interconnect delay = 1.564 ns ( 45.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.475 ns" { CLK CLK~clkctrl ram_dp_ar_aw:m1|mem[2][2] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.475 ns" { CLK CLK~combout CLK~clkctrl ram_dp_ar_aw:m1|mem[2][2] } { 0.000ns 0.000ns 0.474ns 1.090ns } { 0.000ns 1.083ns 0.000ns 0.828ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "13.703 ns" { SRAMADDR[2] ram_dp_ar_aw:m1|mem[1][2]~3355 ram_dp_ar_aw:m1|mem[0][6]~3359 ram_dp_ar_aw:m1|mem[2][4]~3373 ram_dp_ar_aw:m1|mem[2][2] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "13.703 ns" { SRAMADDR[2] SRAMADDR[2]~combout ram_dp_ar_aw:m1|mem[1][2]~3355 ram_dp_ar_aw:m1|mem[0][6]~3359 ram_dp_ar_aw:m1|mem[2][4]~3373 ram_dp_ar_aw:m1|mem[2][2] } { 0.000ns 0.000ns 6.021ns 0.907ns 2.327ns 1.041ns } { 0.000ns 1.134ns 0.464ns 0.302ns 0.507ns 1.000ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.475 ns" { CLK CLK~clkctrl ram_dp_ar_aw:m1|mem[2][2] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.475 ns" { CLK CLK~combout CLK~clkctrl ram_dp_ar_aw:m1|mem[2][2] } { 0.000ns 0.000ns 0.474ns 1.090ns } { 0.000ns 1.083ns 0.000ns 0.828ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK SRAMDATA\[5\] ram_dp_ar_aw:m1\|always1~2 8.775 ns register " "Info: tco from clock \"CLK\" to destination pin \"SRAMDATA\[5\]\" through register \"ram_dp_ar_aw:m1\|always1~2\" is 8.775 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 3.421 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 3.421 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.083 ns) 1.083 ns CLK 1 CLK PIN_A16 1 " "Info: 1: + IC(0.000 ns) + CELL(1.083 ns) = 1.083 ns; Loc. = PIN_A16; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "EPPTOP.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPPTOP.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.474 ns) + CELL(0.000 ns) 1.557 ns CLK~clkctrl 2 COMB CLKCTRL_G15 106 " "Info: 2: + IC(0.474 ns) + CELL(0.000 ns) = 1.557 ns; Loc. = CLKCTRL_G15; Fanout = 106; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.474 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "EPPTOP.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPPTOP.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.036 ns) + CELL(0.828 ns) 3.421 ns ram_dp_ar_aw:m1\|always1~2 3 REG LCFF_X48_Y33_N7 9 " "Info: 3: + IC(1.036 ns) + CELL(0.828 ns) = 3.421 ns; Loc. = LCFF_X48_Y33_N7; Fanout = 9; REG Node = 'ram_dp_ar_aw:m1\|always1~2'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.864 ns" { CLK~clkctrl ram_dp_ar_aw:m1|always1~2 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.911 ns ( 55.86 % ) " "Info: Total cell delay = 1.911 ns ( 55.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.510 ns ( 44.14 % ) " "Info: Total interconnect delay = 1.510 ns ( 44.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.421 ns" { CLK CLK~clkctrl ram_dp_ar_aw:m1|always1~2 } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.421 ns" { CLK CLK~combout CLK~clkctrl ram_dp_ar_aw:m1|always1~2 } { 0.000ns 0.000ns 0.474ns 1.036ns } { 0.000ns 1.083ns 0.000ns 0.828ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.127 ns + " "Info: + Micro clock to output delay of source is 0.127 ns" {  } {  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.227 ns + Longest register pin " "Info: + Longest register to pin delay is 5.227 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ram_dp_ar_aw:m1\|always1~2 1 REG LCFF_X48_Y33_N7 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X48_Y33_N7; Fanout = 9; REG Node = 'ram_dp_ar_aw:m1\|always1~2'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ram_dp_ar_aw:m1|always1~2 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.992 ns) + CELL(0.071 ns) 1.063 ns ram_dp_ar_aw:m1\|data_1_out\[0\]~2128 2 COMB LCCOMB_X46_Y33_N10 8 " "Info: 2: + IC(0.992 ns) + CELL(0.071 ns) = 1.063 ns; Loc. = LCCOMB_X46_Y33_N10; Fanout = 8; COMB Node = 'ram_dp_ar_aw:m1\|data_1_out\[0\]~2128'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.063 ns" { ram_dp_ar_aw:m1|always1~2 ram_dp_ar_aw:m1|data_1_out[0]~2128 } "NODE_NAME" } } { "ram_dp_ar_aw.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/ram_dp_ar_aw.v" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.776 ns) + CELL(2.388 ns) 5.227 ns SRAMDATA\[5\] 3 PIN PIN_K10 0 " "Info: 3: + IC(1.776 ns) + CELL(2.388 ns) = 5.227 ns; Loc. = PIN_K10; Fanout = 0; PIN Node = 'SRAMDATA\[5\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.164 ns" { ram_dp_ar_aw:m1|data_1_out[0]~2128 SRAMDATA[5] } "NODE_NAME" } } { "EPPTOP.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPPTOP.v" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.459 ns ( 47.04 % ) " "Info: Total cell delay = 2.459 ns ( 47.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.768 ns ( 52.96 % ) " "Info: Total interconnect delay = 2.768 ns ( 52.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.227 ns" { ram_dp_ar_aw:m1|always1~2 ram_dp_ar_aw:m1|data_1_out[0]~2128 SRAMDATA[5] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.227 ns" { ram_dp_ar_aw:m1|always1~2 ram_dp_ar_aw:m1|data_1_out[0]~2128 SRAMDATA[5] } { 0.000ns 0.992ns 1.776ns } { 0.000ns 0.071ns 2.388ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.421 ns" { CLK CLK~clkctrl ram_dp_ar_aw:m1|always1~2 } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.421 ns" { CLK CLK~combout CLK~clkctrl ram_dp_ar_aw:m1|always1~2 } { 0.000ns 0.000ns 0.474ns 1.036ns } { 0.000ns 1.083ns 0.000ns 0.828ns } "" } } { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.227 ns" { ram_dp_ar_aw:m1|always1~2 ram_dp_ar_aw:m1|data_1_out[0]~2128 SRAMDATA[5] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.227 ns" { ram_dp_ar_aw:m1|always1~2 ram_dp_ar_aw:m1|data_1_out[0]~2128 SRAMDATA[5] } { 0.000ns 0.992ns 1.776ns } { 0.000ns 0.071ns 2.388ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "SRAMWE SRAMDATA\[5\] 12.980 ns Longest " "Info: Longest tpd from source pin \"SRAMWE\" to destination pin \"SRAMDATA\[5\]\" is 12.980 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.134 ns) 1.134 ns SRAMWE 1 PIN PIN_G10 4 " "Info: 1: + IC(0.000 ns) + CELL(1.134 ns) = 1.134 ns; Loc. = PIN_G10; Fanout = 4; PIN Node = 'SRAMWE'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { SRAMWE } "NODE_NAME" } } { "EPPTOP.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPPTOP.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.839 ns) + CELL(0.302 ns) 7.275 ns ram_dp_ar_aw:m1\|data_1~39 2 COMB LCCOMB_X48_Y32_N10 9 " "Info: 2: + IC(5.839 ns) + CELL(0.302 ns) = 7.275 ns; Loc. = LCCOMB_X48_Y32_N10; Fanout = 9; COMB Node = 'ram_dp_ar_aw:m1\|data_1~39'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.141 ns" { SRAMWE ram_dp_ar_aw:m1|data_1~39 } "NODE_NAME" } } { "ram_dp_ar_aw.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/ram_dp_ar_aw.v" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.177 ns) + CELL(0.364 ns) 8.816 ns ram_dp_ar_aw:m1\|data_1_out\[0\]~2128 3 COMB LCCOMB_X46_Y33_N10 8 " "Info: 3: + IC(1.177 ns) + CELL(0.364 ns) = 8.816 ns; Loc. = LCCOMB_X46_Y33_N10; Fanout = 8; COMB Node = 'ram_dp_ar_aw:m1\|data_1_out\[0\]~2128'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.541 ns" { ram_dp_ar_aw:m1|data_1~39 ram_dp_ar_aw:m1|data_1_out[0]~2128 } "NODE_NAME" } } { "ram_dp_ar_aw.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/ram_dp_ar_aw.v" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.776 ns) + CELL(2.388 ns) 12.980 ns SRAMDATA\[5\] 4 PIN PIN_K10 0 " "Info: 4: + IC(1.776 ns) + CELL(2.388 ns) = 12.980 ns; Loc. = PIN_K10; Fanout = 0; PIN Node = 'SRAMDATA\[5\]'" {  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.164 ns" { ram_dp_ar_aw:m1|data_1_out[0]~2128 SRAMDATA[5] } "NODE_NAME" } } { "EPPTOP.v" "" { Text "D:/montage/verilog code/EPPTOP V1.0/EPPTOP.v" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.188 ns ( 32.27 % ) " "Info: Total cell delay = 4.188 ns ( 32.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.792 ns ( 67.73 % ) " "Info: Total interconnect delay = 8.792 ns ( 67.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "12.980 ns" { SRAMWE ram_dp_ar_aw:m1|data_1~39 ram_dp_ar_aw:m1|data_1_out[0]~2128 SRAMDATA[5] } "NODE_NAME" } } { "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/70/quartus/bin/Technology_Viewer.qrui" "12.980 ns" { SRAMWE SRAMWE~combout ram_dp_ar_aw:m1|data_1~39 ram_dp_ar_aw:m1|data_1_out[0]~2128 SRAMDATA[5] } { 0.000ns 0.000ns 5.839ns 1.177ns 1.776ns } { 0.000ns 1.134ns 0.302ns 0.364ns 2.388ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}