epptop.hier_info

在altera fpga中实现epp模式的并口通信程序

|EPPTOP
WRITE => WRITE~0.IN1
INT <= EPP2SRAM:M0.EPP_Interrupt
WAIT <= EPP2SRAM:M0.EPP_Wait
DS => DS~0.IN1
RST => RST~0.IN2
AS => AS~0.IN1
CLK => CLK~0.IN2
EPPDATA[0] <= EPP2SRAM:M0.EPP_Data
EPPDATA[1] <= EPP2SRAM:M0.EPP_Data
EPPDATA[2] <= EPP2SRAM:M0.EPP_Data
EPPDATA[3] <= EPP2SRAM:M0.EPP_Data
EPPDATA[4] <= EPP2SRAM:M0.EPP_Data
EPPDATA[5] <= EPP2SRAM:M0.EPP_Data
EPPDATA[6] <= EPP2SRAM:M0.EPP_Data
EPPDATA[7] <= EPP2SRAM:M0.EPP_Data
SRAMADDR[0] => SRAMADDR[0]~2.IN1
SRAMADDR[1] => SRAMADDR[1]~1.IN1
SRAMADDR[2] => SRAMADDR[2]~0.IN1
SRAMDATA[0] <= ram_dp_ar_aw:m1.data_1
SRAMDATA[1] <= ram_dp_ar_aw:m1.data_1
SRAMDATA[2] <= ram_dp_ar_aw:m1.data_1
SRAMDATA[3] <= ram_dp_ar_aw:m1.data_1
SRAMDATA[4] <= ram_dp_ar_aw:m1.data_1
SRAMDATA[5] <= ram_dp_ar_aw:m1.data_1
SRAMDATA[6] <= ram_dp_ar_aw:m1.data_1
SRAMDATA[7] <= ram_dp_ar_aw:m1.data_1
SRAMCS => SRAMCS~0.IN1
SRAMWE => SRAMWE~0.IN1
SRAMOE => SRAMOE~0.IN1


|EPPTOP|EPP2SRAM:M0
EPP_Write0 => EPP_Write~0.DATAB
EPP_Write0 => ENV~0.IN1
EPP_Data[0] <= EPP_Data~16
EPP_Data[1] <= EPP_Data~15
EPP_Data[2] <= EPP_Data~14
EPP_Data[3] <= EPP_Data~13
EPP_Data[4] <= EPP_Data~12
EPP_Data[5] <= EPP_Data~11
EPP_Data[6] <= EPP_Data~10
EPP_Data[7] <= EPP_Data~9
EPP_Interrupt <= EPP_Interrupt~reg0.DB_MAX_OUTPUT_PORT_TYPE
EPP_Wait <= EPP_Wait~reg0.DB_MAX_OUTPUT_PORT_TYPE
EPP_DataStrobe0 => EPP_DataStrobe~0.DATAB
EPP_DataStrobe0 => ENV~1.IN0
EPP_Reset0 => EPP_DataStrobe~0.OUTPUTSELECT
EPP_Reset0 => EPP_Write~0.OUTPUTSELECT
EPP_Reset0 => ENV~3.IN0
EPP_Reset0 => EPP_AddressStrobe~0.OUTPUTSELECT
EPP_Reset0 => epp_state~17.OUTPUTSELECT
EPP_Reset0 => epp_state~18.OUTPUTSELECT
EPP_Reset0 => epp_state~19.OUTPUTSELECT
EPP_Reset0 => epp_state~20.OUTPUTSELECT
EPP_Reset0 => epp_state~21.OUTPUTSELECT
EPP_Reset0 => EPP_Wait~3.OUTPUTSELECT
EPP_Reset0 => epp_dataout~40.OUTPUTSELECT
EPP_Reset0 => epp_dataout~41.OUTPUTSELECT
EPP_Reset0 => epp_dataout~42.OUTPUTSELECT
EPP_Reset0 => epp_dataout~43.OUTPUTSELECT
EPP_Reset0 => epp_dataout~44.OUTPUTSELECT
EPP_Reset0 => epp_dataout~45.OUTPUTSELECT
EPP_Reset0 => epp_dataout~46.OUTPUTSELECT
EPP_Reset0 => epp_dataout~47.OUTPUTSELECT
EPP_Reset0 => epp_datain~32.OUTPUTSELECT
EPP_Reset0 => epp_datain~33.OUTPUTSELECT
EPP_Reset0 => epp_datain~34.OUTPUTSELECT
EPP_Reset0 => epp_datain~35.OUTPUTSELECT
EPP_Reset0 => epp_datain~36.OUTPUTSELECT
EPP_Reset0 => epp_datain~37.OUTPUTSELECT
EPP_Reset0 => epp_datain~38.OUTPUTSELECT
EPP_Reset0 => epp_datain~39.OUTPUTSELECT
EPP_Reset0 => SRAM_CE~reg0.DATAIN
EPP_Reset0 => cmd~3.OUTPUTSELECT
EPP_Reset0 => sram_raddr~6.OUTPUTSELECT
EPP_Reset0 => sram_raddr~7.OUTPUTSELECT
EPP_Reset0 => sram_raddr~8.OUTPUTSELECT
EPP_Reset0 => sram_waddr~6.OUTPUTSELECT
EPP_Reset0 => sram_waddr~7.OUTPUTSELECT
EPP_Reset0 => sram_waddr~8.OUTPUTSELECT
EPP_Reset0 => EPP_Interrupt~reg0.ENA
EPP_AddressStrobe0 => EPP_AddressStrobe~0.DATAB
EPP_AddressStrobe0 => ENV~2.IN0
SRAM_CE <= SRAM_CE~reg0.DB_MAX_OUTPUT_PORT_TYPE
SRAM_OE <= cmd[0].DB_MAX_OUTPUT_PORT_TYPE
SRAM_WE <= cmd[0].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[0] <= SRAM_ADDR~2.DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[1] <= SRAM_ADDR~1.DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[2] <= SRAM_ADDR~0.DB_MAX_OUTPUT_PORT_TYPE
SRAM_DATA[0] <= SRAM_DATA~15
SRAM_DATA[1] <= SRAM_DATA~14
SRAM_DATA[2] <= SRAM_DATA~13
SRAM_DATA[3] <= SRAM_DATA~12
SRAM_DATA[4] <= SRAM_DATA~11
SRAM_DATA[5] <= SRAM_DATA~10
SRAM_DATA[6] <= SRAM_DATA~9
SRAM_DATA[7] <= SRAM_DATA~8
ENV <= ENV~3.DB_MAX_OUTPUT_PORT_TYPE
clk => EPP_DataStrobe.CLK
clk => EPP_AddressStrobe.CLK
clk => EPP_Interrupt~reg0.CLK
clk => EPP_Wait~reg0.CLK
clk => epp_dataout[7].CLK
clk => epp_dataout[6].CLK
clk => epp_dataout[5].CLK
clk => epp_dataout[4].CLK
clk => epp_dataout[3].CLK
clk => epp_dataout[2].CLK
clk => epp_dataout[1].CLK
clk => epp_dataout[0].CLK
clk => epp_datain[7].CLK
clk => epp_datain[6].CLK
clk => epp_datain[5].CLK
clk => epp_datain[4].CLK
clk => epp_datain[3].CLK
clk => epp_datain[2].CLK
clk => epp_datain[1].CLK
clk => epp_datain[0].CLK
clk => cmd[0].CLK
clk => sram_raddr[2].CLK
clk => sram_raddr[1].CLK
clk => sram_raddr[0].CLK
clk => sram_waddr[2].CLK
clk => sram_waddr[1].CLK
clk => sram_waddr[0].CLK
clk => SRAM_CE~reg0.CLK
clk => EPP_Write.CLK
clk => epp_state~22.IN1


|EPPTOP|ram_dp_ar_aw:m1
address_0[0] => Decoder0.IN2
address_0[0] => Mux0.IN3
address_0[0] => Mux1.IN3
address_0[0] => Mux2.IN3
address_0[0] => Mux3.IN3
address_0[0] => Mux4.IN3
address_0[0] => Mux5.IN3
address_0[0] => Mux6.IN3
address_0[0] => Mux7.IN3
address_0[1] => Decoder0.IN1
address_0[1] => Mux0.IN2
address_0[1] => Mux1.IN2
address_0[1] => Mux2.IN2
address_0[1] => Mux3.IN2
address_0[1] => Mux4.IN2
address_0[1] => Mux5.IN2
address_0[1] => Mux6.IN2
address_0[1] => Mux7.IN2
address_0[2] => Decoder0.IN0
address_0[2] => Mux0.IN1
address_0[2] => Mux1.IN1
address_0[2] => Mux2.IN1
address_0[2] => Mux3.IN1
address_0[2] => Mux4.IN1
address_0[2] => Mux5.IN1
address_0[2] => Mux6.IN1
address_0[2] => Mux7.IN1
data_0[0] <= data_0~17
data_0[1] <= data_0~16
data_0[2] <= data_0~15
data_0[3] <= data_0~14
data_0[4] <= data_0~13
data_0[5] <= data_0~12
data_0[6] <= data_0~11
data_0[7] <= data_0~10
cs_0 => data_0~8.IN0
cs_0 => always0~0.IN1
cs_0 => always1~0.IN1
we_0 => always1~0.IN0
we_0 => data_0~9.IN0
we_0 => always0~0.IN0
oe_0 => always0~1.IN1
oe_0 => data_0~8.IN1
oe_0 => always1~1.IN0
address_1[0] => Decoder1.IN2
address_1[0] => Mux8.IN3
address_1[0] => Mux9.IN3
address_1[0] => Mux10.IN3
address_1[0] => Mux11.IN3
address_1[0] => Mux12.IN3
address_1[0] => Mux13.IN3
address_1[0] => Mux14.IN3
address_1[0] => Mux15.IN3
address_1[1] => Decoder1.IN1
address_1[1] => Mux8.IN2
address_1[1] => Mux9.IN2
address_1[1] => Mux10.IN2
address_1[1] => Mux11.IN2
address_1[1] => Mux12.IN2
address_1[1] => Mux13.IN2
address_1[1] => Mux14.IN2
address_1[1] => Mux15.IN2
address_1[2] => Decoder1.IN0
address_1[2] => Mux8.IN1
address_1[2] => Mux9.IN1
address_1[2] => Mux10.IN1
address_1[2] => Mux11.IN1
address_1[2] => Mux12.IN1
address_1[2] => Mux13.IN1
address_1[2] => Mux14.IN1
address_1[2] => Mux15.IN1
data_1[0] <= data_1~17
data_1[1] <= data_1~16
data_1[2] <= data_1~15
data_1[3] <= data_1~14
data_1[4] <= data_1~13
data_1[5] <= data_1~12
data_1[6] <= data_1~11
data_1[7] <= data_1~10
cs_1 => data_1~8.IN0
cs_1 => always0~2.IN1
cs_1 => always2~0.IN1
we_1 => always2~0.IN0
we_1 => data_1~9.IN0
we_1 => always0~2.IN0
oe_1 => always0~3.IN1
oe_1 => data_1~8.IN1
oe_1 => always2~1.IN0
sclk => mem[0][6].CLK
sclk => mem[0][5].CLK
sclk => mem[0][4].CLK
sclk => mem[0][3].CLK
sclk => mem[0][2].CLK
sclk => mem[0][1].CLK
sclk => mem[0][0].CLK
sclk => mem[1][7].CLK
sclk => mem[1][6].CLK
sclk => mem[1][5].CLK
sclk => mem[1][4].CLK
sclk => mem[1][3].CLK
sclk => mem[1][2].CLK
sclk => mem[1][1].CLK
sclk => mem[1][0].CLK
sclk => mem[2][7].CLK
sclk => mem[2][6].CLK
sclk => mem[2][5].CLK
sclk => mem[2][4].CLK
sclk => mem[2][3].CLK
sclk => mem[2][2].CLK
sclk => mem[2][1].CLK
sclk => mem[2][0].CLK
sclk => mem[3][7].CLK
sclk => mem[3][6].CLK
sclk => mem[3][5].CLK
sclk => mem[3][4].CLK
sclk => mem[3][3].CLK
sclk => mem[3][2].CLK
sclk => mem[3][1].CLK
sclk => mem[3][0].CLK
sclk => mem[4][7].CLK
sclk => mem[4][6].CLK
sclk => mem[4][5].CLK
sclk => mem[4][4].CLK
sclk => mem[4][3].CLK
sclk => mem[4][2].CLK
sclk => mem[4][1].CLK
sclk => mem[4][0].CLK
sclk => mem[5][7].CLK
sclk => mem[5][6].CLK
sclk => mem[5][5].CLK
sclk => mem[5][4].CLK
sclk => mem[5][3].CLK
sclk => mem[5][2].CLK
sclk => mem[5][1].CLK
sclk => mem[5][0].CLK
sclk => mem[6][7].CLK
sclk => mem[6][6].CLK
sclk => mem[6][5].CLK
sclk => mem[6][4].CLK
sclk => mem[6][3].CLK
sclk => mem[6][2].CLK
sclk => mem[6][1].CLK
sclk => mem[6][0].CLK
sclk => data_0_out[7].CLK
sclk => data_0_out[6].CLK
sclk => data_0_out[5].CLK
sclk => data_0_out[4].CLK
sclk => data_0_out[3].CLK
sclk => data_0_out[2].CLK
sclk => data_0_out[1].CLK
sclk => data_0_out[0].CLK
sclk => always1~2.CLK
sclk => always1~4.CLK
sclk => always1~5.CLK
sclk => always1~6.CLK
sclk => always1~7.CLK
sclk => always1~8.CLK
sclk => always1~9.CLK
sclk => always1~10.CLK
sclk => data_1_out[7].CLK
sclk => data_1_out[6].CLK
sclk => data_1_out[5].CLK
sclk => data_1_out[4].CLK
sclk => data_1_out[3].CLK
sclk => data_1_out[2].CLK
sclk => data_1_out[1].CLK
sclk => data_1_out[0].CLK
sclk => always2~2.CLK
sclk => always2~3.CLK
sclk => always2~4.CLK
sclk => always2~5.CLK
sclk => always2~6.CLK
sclk => always2~7.CLK
sclk => always2~8.CLK
sclk => always2~9.CLK
sclk => mem[0][7].CLK
SENV => mem~224.OUTPUTSELECT
SENV => mem~225.OUTPUTSELECT
SENV => mem~226.OUTPUTSELECT
SENV => mem~227.OUTPUTSELECT
SENV => mem~228.OUTPUTSELECT
SENV => mem~229.OUTPUTSELECT
SENV => mem~230.OUTPUTSELECT
SENV => mem~231.OUTPUTSELECT
SENV => mem~232.OUTPUTSELECT
SENV => mem~233.OUTPUTSELECT
SENV => mem~234.OUTPUTSELECT
SENV => mem~235.OUTPUTSELECT
SENV => mem~236.OUTPUTSELECT
SENV => mem~237.OUTPUTSELECT
SENV => mem~238.OUTPUTSELECT
SENV => mem~239.OUTPUTSELECT
SENV => mem~240.OUTPUTSELECT
SENV => mem~241.OUTPUTSELECT
SENV => mem~242.OUTPUTSELECT
SENV => mem~243.OUTPUTSELECT
SENV => mem~244.OUTPUTSELECT
SENV => mem~245.OUTPUTSELECT
SENV => mem~246.OUTPUTSELECT
SENV => mem~247.OUTPUTSELECT
SENV => mem~248.OUTPUTSELECT
SENV => mem~249.OUTPUTSELECT
SENV => mem~250.OUTPUTSELECT
SENV => mem~251.OUTPUTSELECT
SENV => mem~252.OUTPUTSELECT
SENV => mem~253.OUTPUTSELECT
SENV => mem~254.OUTPUTSELECT
SENV => mem~255.OUTPUTSELECT
SENV => mem~256.OUTPUTSELECT
SENV => mem~257.OUTPUTSELECT
SENV => mem~258.OUTPUTSELECT
SENV => mem~259.OUTPUTSELECT
SENV => mem~260.OUTPUTSELECT
SENV => mem~261.OUTPUTSELECT
SENV => mem~262.OUTPUTSELECT
SENV => mem~263.OUTPUTSELECT
SENV => mem~264.OUTPUTSELECT
SENV => mem~265.OUTPUTSELECT
SENV => mem~266.OUTPUTSELECT
SENV => mem~267.OUTPUTSELECT
SENV => mem~268.OUTPUTSELECT
SENV => mem~269.OUTPUTSELECT
SENV => mem~270.OUTPUTSELECT
SENV => mem~271.OUTPUTSELECT
SENV => mem~272.OUTPUTSELECT
SENV => mem~273.OUTPUTSELECT
SENV => mem~274.OUTPUTSELECT
SENV => mem~275.OUTPUTSELECT
SENV => mem~276.OUTPUTSELECT
SENV => mem~277.OUTPUTSELECT
SENV => mem~278.OUTPUTSELECT
SENV => mem~279.OUTPUTSELECT
SENV => always1~3.IN0
RESET => always1~3.IN1
RESET => mem~280.OUTPUTSELECT
RESET => mem~281.OUTPUTSELECT
RESET => mem~282.OUTPUTSELECT
RESET => mem~283.OUTPUTSELECT
RESET => mem~284.OUTPUTSELECT
RESET => mem~285.OUTPUTSELECT
RESET => mem~286.OUTPUTSELECT
RESET => mem~287.OUTPUTSELECT
RESET => mem~288.OUTPUTSELECT
RESET => mem~289.OUTPUTSELECT
RESET => mem~290.OUTPUTSELECT
RESET => mem~291.OUTPUTSELECT
RESET => mem~292.OUTPUTSELECT
RESET => mem~293.OUTPUTSELECT
RESET => mem~294.OUTPUTSELECT
RESET => mem~295.OUTPUTSELECT
RESET => mem~296.OUTPUTSELECT
RESET => mem~297.OUTPUTSELECT
RESET => mem~298.OUTPUTSELECT
RESET => mem~299.OUTPUTSELECT
RESET => mem~300.OUTPUTSELECT
RESET => mem~301.OUTPUTSELECT
RESET => mem~302.OUTPUTSELECT
RESET => mem~303.OUTPUTSELECT
RESET => mem~304.OUTPUTSELECT
RESET => mem~305.OUTPUTSELECT
RESET => mem~306.OUTPUTSELECT
RESET => mem~307.OUTPUTSELECT
RESET => mem~308.OUTPUTSELECT
RESET => mem~309.OUTPUTSELECT
RESET => mem~310.OUTPUTSELECT
RESET => mem~311.OUTPUTSELECT
RESET => mem~312.OUTPUTSELECT
RESET => mem~313.OUTPUTSELECT
RESET => mem~314.OUTPUTSELECT
RESET => mem~315.OUTPUTSELECT
RESET => mem~316.OUTPUTSELECT
RESET => mem~317.OUTPUTSELECT
RESET => mem~318.OUTPUTSELECT
RESET => mem~319.OUTPUTSELECT
RESET => mem~320.OUTPUTSELECT
RESET => mem~321.OUTPUTSELECT
RESET => mem~322.OUTPUTSELECT
RESET => mem~323.OUTPUTSELECT
RESET => mem~324.OUTPUTSELECT
RESET => mem~325.OUTPUTSELECT
RESET => mem~326.OUTPUTSELECT
RESET => mem~327.OUTPUTSELECT
RESET => mem~328.OUTPUTSELECT
RESET => mem~329.OUTPUTSELECT
RESET => mem~330.OUTPUTSELECT
RESET => mem~331.OUTPUTSELECT
RESET => mem~332.OUTPUTSELECT
RESET => mem~333.OUTPUTSELECT
RESET => mem~334.OUTPUTSELECT
RESET => mem~335.OUTPUTSELECT