epptop.fit.eqn

在altera fpga中实现epp模式的并口通信程序

--B1L28 is EPP2SRAM:M0|sram_raddr[0]~19 at LCCOMB_X10_Y6_N28
B1L28 = B1_epp_state.EPP_WAIT_DATAREAD # !RST;


--B1L44 is EPP2SRAM:M0|epp_datain~74 at LCCOMB_X8_Y7_N12
B1L44 = RST & A1L71;


--C1L12 is ram_dp_ar_aw:m1|data_0_out[1]~141 at LCCOMB_X5_Y6_N18
C1L12 = B1L01 & B1L11 # !B1L01 & B1L11 & C1_mem[4][1] # !B1L11 & C1_mem[0][1];


--C1L22 is ram_dp_ar_aw:m1|data_0_out[1]~142 at LCCOMB_X7_Y6_N26
C1L22 = B1L01 & C1L12 & C1_mem[6][1] # !C1L12 & C1_mem[2][1] # !B1L01 & C1L12;


--C1L32 is ram_dp_ar_aw:m1|data_0_out[1]~143 at LCCOMB_X7_Y6_N18
C1L32 = C1L55 & !C1L65 # !C1L55 & C1L65 & C1_mem[1][1] # !C1L65 & C1L22;


--C1L42 is ram_dp_ar_aw:m1|data_0_out[1]~144 at LCCOMB_X6_Y5_N26
C1L42 = C1L55 & C1L32 & C1_mem[3][1] # !C1L32 & C1_mem[5][1] # !C1L55 & C1L32;


--C1L46 is ram_dp_ar_aw:m1|data_0_out~115 at LCCOMB_X6_Y5_N18
C1L46 = !B1_cmd[0] & !B1_SRAM_CE & C1L42;


--B1L22 is EPP2SRAM:M0|add~82 at LCCOMB_X9_Y5_N6
B1L22 = B1_sram_waddr[1] $ (B1_EPP_DataStrobe & B1_sram_waddr[0]);


--B1L91 is EPP2SRAM:M0|add~67 at LCCOMB_X9_Y5_N10
B1L91 = B1_sram_raddr[1] $ (B1_EPP_DataStrobe & B1_sram_raddr[0]);


--B1L54 is EPP2SRAM:M0|epp_datain~75 at LCCOMB_X8_Y7_N30
B1L54 = A1L51 & RST;


--C1L61 is ram_dp_ar_aw:m1|data_0_out[0]~145 at LCCOMB_X6_Y6_N18
C1L61 = B1L01 & B1L11 # C1_mem[2][0] # !B1L01 & !B1L11 & C1_mem[0][0];


--C1L71 is ram_dp_ar_aw:m1|data_0_out[0]~146 at LCCOMB_X7_Y4_N20
C1L71 = B1L11 & C1L61 & C1_mem[6][0] # !C1L61 & C1_mem[4][0] # !B1L11 & C1L61;


--C1L81 is ram_dp_ar_aw:m1|data_0_out[0]~147 at LCCOMB_X6_Y5_N6
C1L81 = C1L55 & C1_mem[5][0] # !C1L65 # !C1L55 & C1_mem[1][0] & C1L65;


--C1L91 is ram_dp_ar_aw:m1|data_0_out[0]~148 at LCCOMB_X6_Y5_N4
C1L91 = C1L81 & C1_mem[3][0] # C1L65 # !C1L81 & C1L71 & !C1L65;


--C1L56 is ram_dp_ar_aw:m1|data_0_out~116 at LCCOMB_X6_Y5_N30
C1L56 = !B1_cmd[0] & !B1_SRAM_CE & C1L91;


--B1L12 is EPP2SRAM:M0|add~77 at LCCOMB_X9_Y5_N2
B1L12 = B1_EPP_DataStrobe $ B1_sram_waddr[0];


--B1L81 is EPP2SRAM:M0|add~62 at LCCOMB_X9_Y5_N0
B1L81 = B1_EPP_DataStrobe $ B1_sram_raddr[0];


--C1L1 is ram_dp_ar_aw:m1|always0~1 at LCCOMB_X8_Y6_N8
C1L1 = !B1_SRAM_CE & B1_cmd[0];


--C1L031 is ram_dp_ar_aw:m1|mem[0]~4070 at LCCOMB_X7_Y6_N16
C1L031 = C1L4 & C1L1 & A1L8 # !C1L1 & A1L35;


--C1L2 is ram_dp_ar_aw:m1|always0~179 at LCCOMB_X5_Y6_N0
C1L2 = !SRAMWE & !SRAMCS & SRAMOE;


--C1L881 is ram_dp_ar_aw:m1|mem[5][0]~4071 at LCCOMB_X5_Y6_N24
C1L881 = SRAMADDR[1] # !C1L2 # !SRAMADDR[2] # !SRAMADDR[0];


--C1L75 is ram_dp_ar_aw:m1|data_0_out[7]~325 at LCCOMB_X9_Y6_N20
C1L75 = !B1L01 & B1L11 & B1L9;


--C1L981 is ram_dp_ar_aw:m1|mem[5][0]~4072 at LCCOMB_X8_Y6_N4
C1L981 = C1L1 & C1L75 # !C1L1 & !C1L881 # !C1L4;


--C1L551 is ram_dp_ar_aw:m1|mem[2][3]~4073 at LCCOMB_X9_Y6_N24
C1L551 = B1L11 # B1L9 # !B1L01;


--C1L651 is ram_dp_ar_aw:m1|mem[2][3]~4074 at LCCOMB_X5_Y6_N2
C1L651 = SRAMADDR[0] # SRAMADDR[2] # !C1L2 # !SRAMADDR[1];


--C1L751 is ram_dp_ar_aw:m1|mem[2][3]~4075 at LCCOMB_X8_Y6_N18
C1L751 = C1L1 & !C1L551 # !C1L1 & !C1L651 # !C1L4;


--C1L671 is ram_dp_ar_aw:m1|mem[4][0]~4076 at LCCOMB_X9_Y6_N14
C1L671 = B1L01 # B1L9 # !B1L11;


--C1L771 is ram_dp_ar_aw:m1|mem[4][0]~4077 at LCCOMB_X5_Y6_N4
C1L771 = SRAMADDR[1] # SRAMADDR[0] # !C1L2 # !SRAMADDR[2];


--C1L871 is ram_dp_ar_aw:m1|mem[4][0]~4078 at LCCOMB_X8_Y6_N30
C1L871 = C1L1 & !C1L671 # !C1L1 & !C1L771 # !C1L4;


--C1L521 is ram_dp_ar_aw:m1|mem[0][5]~4079 at LCCOMB_X9_Y6_N12
C1L521 = B1L01 # B1L11 # B1L9;


--C1L621 is ram_dp_ar_aw:m1|mem[0][5]~4080 at LCCOMB_X5_Y6_N26
C1L621 = SRAMADDR[1] # SRAMADDR[0] # SRAMADDR[2] # !C1L2;


--C1L721 is ram_dp_ar_aw:m1|mem[0][5]~4081 at LCCOMB_X8_Y6_N20
C1L721 = C1L1 & !C1L521 # !C1L1 & !C1L621 # !C1L4;


--C1L402 is ram_dp_ar_aw:m1|mem[6][5]~4082 at LCCOMB_X9_Y6_N26
C1L402 = B1L9 # !B1L11 # !B1L01;


--C1L502 is ram_dp_ar_aw:m1|mem[6][5]~4083 at LCCOMB_X5_Y6_N30
C1L502 = SRAMADDR[0] # !C1L2 # !SRAMADDR[2] # !SRAMADDR[1];


--C1L602 is ram_dp_ar_aw:m1|mem[6][5]~4084 at LCCOMB_X8_Y6_N12
C1L602 = C1L1 & !C1L402 # !C1L1 & !C1L502 # !C1L4;


--C1L041 is ram_dp_ar_aw:m1|mem[1][0]~4085 at LCCOMB_X9_Y6_N28
C1L041 = B1L01 # B1L11 # !B1L9;


--C1L141 is ram_dp_ar_aw:m1|mem[1][0]~4086 at LCCOMB_X5_Y6_N12
C1L141 = SRAMADDR[1] # SRAMADDR[2] # !C1L2 # !SRAMADDR[0];


--C1L241 is ram_dp_ar_aw:m1|mem[1][0]~4087 at LCCOMB_X8_Y6_N24
C1L241 = C1L1 & !C1L041 # !C1L1 & !C1L141 # !C1L4;


--C1L461 is ram_dp_ar_aw:m1|mem[3][0]~4088 at LCCOMB_X9_Y6_N4
C1L461 = B1L11 # !B1L9 # !B1L01;


--C1L561 is ram_dp_ar_aw:m1|mem[3][0]~4089 at LCCOMB_X5_Y6_N6
C1L561 = SRAMADDR[2] # !C1L2 # !SRAMADDR[0] # !SRAMADDR[1];


--C1L661 is ram_dp_ar_aw:m1|mem[3][0]~4090 at LCCOMB_X9_Y6_N8
C1L661 = C1L1 & !C1L461 # !C1L1 & !C1L561 # !C1L4;


--C1L131 is ram_dp_ar_aw:m1|mem[0]~4091 at LCCOMB_X8_Y5_N30
C1L131 = C1L4 & C1L1 & A1L7 # !C1L1 & A1L15;


--C1L231 is ram_dp_ar_aw:m1|mem[0]~4092 at LCCOMB_X7_Y4_N28
C1L231 = C1L4 & C1L1 & A1L6 # !C1L1 & A1L94;


--C1L331 is ram_dp_ar_aw:m1|mem[0]~4093 at LCCOMB_X8_Y5_N24
C1L331 = C1L4 & C1L1 & A1L5 # !C1L1 & A1L74;


--C1L431 is ram_dp_ar_aw:m1|mem[0]~4094 at LCCOMB_X8_Y6_N0
C1L431 = C1L4 & C1L1 & A1L4 # !C1L1 & A1L54;


--C1L531 is ram_dp_ar_aw:m1|mem[0]~4095 at LCCOMB_X6_Y4_N18
C1L531 = C1L4 & C1L1 & A1L3 # !C1L1 & A1L34;


--C1L631 is ram_dp_ar_aw:m1|mem[0]~4096 at LCCOMB_X5_Y5_N0
C1L631 = C1L4 & C1L1 & A1L2 # !C1L1 & A1L14;


--C1L731 is ram_dp_ar_aw:m1|mem[0]~4097 at LCCOMB_X8_Y6_N26
C1L731 = C1L4 & C1L1 & A1L1 # !C1L1 & A1L93;


--B1L03 is EPP2SRAM:M0|epp_datain[0]~156 at LCCOMB_X10_Y7_N30
B1L03 = !B1_epp_state.EPP_IDLE & !B1_EPP_Write & B1L47 # !RST;


--B1L31 is EPP2SRAM:M0|SRAM_CE~9 at LCCOMB_X8_Y6_N6
B1L31 = !RST;


--CLK is CLK at PIN_17
--operation mode is input

CLK = INPUT();


--RST is RST at PIN_24
--operation mode is input

RST = INPUT();


--DS is DS at PIN_59
--operation mode is input

DS = INPUT();


--AS is AS at PIN_126
--operation mode is input

AS = INPUT();


--SRAMWE is SRAMWE at PIN_25
--operation mode is input

SRAMWE = INPUT();


--SRAMCS is SRAMCS at PIN_18
--operation mode is input

SRAMCS = INPUT();


--SRAMOE is SRAMOE at PIN_21
--operation mode is input

SRAMOE = INPUT();


--WRITE is WRITE at PIN_22
--operation mode is input

WRITE = INPUT();


--SRAMADDR[0] is SRAMADDR[0] at PIN_8
--operation mode is input

SRAMADDR[0] = INPUT();


--SRAMADDR[2] is SRAMADDR[2] at PIN_32
--operation mode is input

SRAMADDR[2] = INPUT();


--SRAMADDR[1] is SRAMADDR[1] at PIN_26
--operation mode is input

SRAMADDR[1] = INPUT();


--INT is INT at PIN_67
--operation mode is output

INT = OUTPUT(GND);


--WAIT is WAIT at PIN_135
--operation mode is output

WAIT = OUTPUT(B1_EPP_Wait);


--A1L92 is EPPDATA[7]~0 at PIN_133
--operation mode is bidir

A1L92 = EPPDATA[7];

--EPPDATA[7] is EPPDATA[7] at PIN_133
--operation mode is bidir

EPPDATA[7]_tri_out = TRI(B1_epp_dataout[7], B1L5);
EPPDATA[7] = BIDIR(EPPDATA[7]_tri_out);


--A1L72 is EPPDATA[6]~1 at PIN_129
--operation mode is bidir

A1L72 = EPPDATA[6];

--EPPDATA[6] is EPPDATA[6] at PIN_129
--operation mode is bidir

EPPDATA[6]_tri_out = TRI(B1_epp_dataout[6], B1L5);
EPPDATA[6] = BIDIR(EPPDATA[6]_tri_out);


--A1L52 is EPPDATA[5]~2 at PIN_57
--operation mode is bidir

A1L52 = EPPDATA[5];

--EPPDATA[5] is EPPDATA[5] at PIN_57
--operation mode is bidir

EPPDATA[5]_tri_out = TRI(B1_epp_dataout[5], B1L5);
EPPDATA[5] = BIDIR(EPPDATA[5]_tri_out);


--A1L32 is EPPDATA[4]~3 at PIN_134
--operation mode is bidir

A1L32 = EPPDATA[4];

--EPPDATA[4] is EPPDATA[4] at PIN_134
--operation mode is bidir

EPPDATA[4]_tri_out = TRI(B1_epp_dataout[4], B1L5);
EPPDATA[4] = BIDIR(EPPDATA[4]_tri_out);


--A1L12 is EPPDATA[3]~4 at PIN_55
--operation mode is bidir

A1L12 = EPPDATA[3];

--EPPDATA[3] is EPPDATA[3] at PIN_55
--operation mode is bidir

EPPDATA[3]_tri_out = TRI(B1_epp_dataout[3], B1L5);
EPPDATA[3] = BIDIR(EPPDATA[3]_tri_out);


--A1L91 is EPPDATA[2]~5 at PIN_53
--operation mode is bidir

A1L91 = EPPDATA[2];

--EPPDATA[2] is EPPDATA[2] at PIN_53
--operation mode is bidir

EPPDATA[2]_tri_out = TRI(B1_epp_dataout[2], B1L5);
EPPDATA[2] = BIDIR(EPPDATA[2]_tri_out);


--A1L71 is EPPDATA[1]~6 at PIN_52
--operation mode is bidir

A1L71 = EPPDATA[1];

--EPPDATA[1] is EPPDATA[1] at PIN_52
--operation mode is bidir

EPPDATA[1]_tri_out = TRI(B1_epp_dataout[1], B1L5);
EPPDATA[1] = BIDIR(EPPDATA[1]_tri_out);


--A1L51 is EPPDATA[0]~7 at PIN_58
--operation mode is bidir

A1L51 = EPPDATA[0];

--EPPDATA[0] is EPPDATA[0] at PIN_58
--operation mode is bidir

EPPDATA[0]_tri_out = TRI(B1_epp_dataout[0], B1L5);
EPPDATA[0] = BIDIR(EPPDATA[0]_tri_out);


--A1L35 is SRAMDATA[7]~0 at PIN_48
--operation mode is bidir

A1L35 = SRAMDATA[7];

--SRAMDATA[7] is SRAMDATA[7] at PIN_48
--operation mode is bidir

SRAMDATA[7]_tri_out = TRI(C1L6, C1L711);
SRAMDATA[7] = BIDIR(SRAMDATA[7]_tri_out);


--A1L15 is SRAMDATA[6]~1 at PIN_27
--operation mode is bidir

A1L15 = SRAMDATA[6];

--SRAMDATA[6] is SRAMDATA[6] at PIN_27
--operation mode is bidir

SRAMDATA[6]_tri_out = TRI(C1L7, C1L711);
SRAMDATA[6] = BIDIR(SRAMDATA[6]_tri_out);


--A1L94 is SRAMDATA[5]~2 at PIN_44
--operation mode is bidir

A1L94 = SRAMDATA[5];

--SRAMDATA[5] is SRAMDATA[5] at PIN_44
--operation mode is bidir

SRAMDATA[5]_tri_out = TRI(C1L8, C1L711);
SRAMDATA[5] = BIDIR(SRAMDATA[5]_tri_out);


--A1L74 is SRAMDATA[4]~3 at PIN_41
--operation mode is bidir

A1L74 = SRAMDATA[4];

--SRAMDATA[4] is SRAMDATA[4] at PIN_41
--operation mode is bidir

SRAMDATA[4]_tri_out = TRI(C1L9, C1L711);
SRAMDATA[4] = BIDIR(SRAMDATA[4]_tri_out);


--A1L54 is SRAMDATA[3]~4 at PIN_45
--operation mode is bidir

A1L54 = SRAMDATA[3];

--SRAMDATA[3] is SRAMDATA[3] at PIN_45
--operation mode is bidir

SRAMDATA[3]_tri_out = TRI(C1L01, C1L711);
SRAMDATA[3] = BIDIR(SRAMDATA[3]_tri_out);


--A1L34 is SRAMDATA[2]~5 at PIN_28
--operation mode is bidir

A1L34 = SRAMDATA[2];

--SRAMDATA[2] is SRAMDATA[2] at PIN_28
--operation mode is bidir

SRAMDATA[2]_tri_out = TRI(C1L11, C1L711);
SRAMDATA[2] = BIDIR(SRAMDATA[2]_tri_out);


--A1L14 is SRAMDATA[1]~6 at PIN_42
--operation mode is bidir

A1L14 = SRAMDATA[1];

--SRAMDATA[1] is SRAMDATA[1] at PIN_42
--operation mode is bidir

SRAMDATA[1]_tri_out = TRI(C1L21, C1L711);
SRAMDATA[1] = BIDIR(SRAMDATA[1]_tri_out);


--A1L93 is SRAMDATA[0]~7 at PIN_47
--operation mode is bidir

A1L93 = SRAMDATA[0];

--SRAMDATA[0] is SRAMDATA[0] at PIN_47
--operation mode is bidir

SRAMDATA[0]_tri_out = TRI(C1L31, C1L711);
SRAMDATA[0] = BIDIR(SRAMDATA[0]_tri_out);





--A1L11 is CLK~clkctrl at CLKCTRL_G2
A1L11 = cycloneii_clkctrl(.INCLK[0] = CLK) WITH (clock_type = "Global Clock");