epptop.fit.eqn

在altera fpga中实现epp模式的并口通信程序

--B1_EPP_Wait is EPP2SRAM:M0|EPP_Wait at LCFF_X10_Y6_N3
B1_EPP_Wait = DFFEAS(B1L71, GLOBAL(A1L11),  ,  ,  ,  ,  , !RST,  );


--B1_EPP_DataStrobe is EPP2SRAM:M0|EPP_DataStrobe at LCFF_X10_Y7_N25
B1_EPP_DataStrobe = DFFEAS(B1L4, GLOBAL(A1L11),  ,  ,  ,  ,  ,  ,  );


--B1_EPP_AddressStrobe is EPP2SRAM:M0|EPP_AddressStrobe at LCFF_X10_Y7_N5
B1_EPP_AddressStrobe = DFFEAS(B1L2, GLOBAL(A1L11),  ,  ,  ,  ,  ,  ,  );


--B1_epp_state.EPP_WAIT_ADDRWRITE is EPP2SRAM:M0|epp_state.EPP_WAIT_ADDRWRITE at LCFF_X10_Y7_N21
B1_epp_state.EPP_WAIT_ADDRWRITE = DFFEAS(B1L27, GLOBAL(A1L11),  ,  ,  ,  ,  ,  ,  );


--B1_epp_state.EPP_WAIT_ADDRREAD is EPP2SRAM:M0|epp_state.EPP_WAIT_ADDRREAD at LCFF_X10_Y7_N7
B1_epp_state.EPP_WAIT_ADDRREAD = DFFEAS(B1L37, GLOBAL(A1L11),  ,  ,  ,  ,  ,  ,  );


--B1L41 is EPP2SRAM:M0|Select~208 at LCCOMB_X10_Y7_N16
B1L41 = !B1_epp_state.EPP_WAIT_ADDRWRITE & !B1_epp_state.EPP_WAIT_ADDRREAD;


--B1_epp_state.EPP_WAIT_DATAWRITE is EPP2SRAM:M0|epp_state.EPP_WAIT_DATAWRITE at LCFF_X10_Y7_N15
B1_epp_state.EPP_WAIT_DATAWRITE = DFFEAS(B1L67, GLOBAL(A1L11),  ,  ,  ,  ,  ,  ,  );


--B1_epp_state.EPP_WAIT_DATAREAD is EPP2SRAM:M0|epp_state.EPP_WAIT_DATAREAD at LCFF_X10_Y7_N13
B1_epp_state.EPP_WAIT_DATAREAD = DFFEAS(B1L77, GLOBAL(A1L11),  ,  ,  ,  ,  ,  ,  );


--B1L51 is EPP2SRAM:M0|Select~209 at LCCOMB_X10_Y7_N8
B1L51 = !B1_epp_state.EPP_WAIT_DATAWRITE & !B1_epp_state.EPP_WAIT_DATAREAD;


--B1L61 is EPP2SRAM:M0|Select~210 at LCCOMB_X10_Y6_N26
B1L61 = B1_EPP_AddressStrobe & !B1_EPP_DataStrobe & !B1L51 # !B1_EPP_AddressStrobe & !B1_EPP_DataStrobe & !B1L51 # !B1L41;


--B1_epp_state.EPP_IDLE is EPP2SRAM:M0|epp_state.EPP_IDLE at LCFF_X10_Y7_N29
B1_epp_state.EPP_IDLE = DFFEAS(B1L97, GLOBAL(A1L11),  ,  ,  ,  ,  ,  ,  );


--B1L96 is EPP2SRAM:M0|epp_state~666 at LCCOMB_X10_Y7_N2
B1L96 = B1_EPP_AddressStrobe & B1_EPP_DataStrobe;


--B1L71 is EPP2SRAM:M0|Select~211 at LCCOMB_X10_Y6_N2
B1L71 = B1_epp_state.EPP_IDLE & B1L61 & B1_EPP_Wait # !B1_epp_state.EPP_IDLE & B1L61 & B1_EPP_Wait # !B1L96;


--B1L4 is EPP2SRAM:M0|EPP_DataStrobe~3 at LCCOMB_X10_Y7_N24
B1L4 = DS # !RST;


--B1L2 is EPP2SRAM:M0|EPP_AddressStrobe~3 at LCCOMB_X10_Y7_N4
B1L2 = AS # !RST;


--B1L07 is EPP2SRAM:M0|epp_state~667 at LCCOMB_X10_Y7_N10
B1L07 = B1L41 & B1L51 # !B1_EPP_DataStrobe # !B1L41 & !B1_EPP_AddressStrobe & B1L51 # !B1_EPP_DataStrobe;


--B1L17 is EPP2SRAM:M0|epp_state~668 at LCCOMB_X10_Y7_N0
B1L17 = RST & B1_epp_state.EPP_IDLE & B1L07 # !B1_epp_state.EPP_IDLE & !B1_EPP_AddressStrobe;


--B1_EPP_Write is EPP2SRAM:M0|EPP_Write at LCFF_X8_Y7_N17
B1_EPP_Write = DFFEAS(B1L8, GLOBAL(A1L11),  ,  ,  ,  ,  ,  ,  );


--B1L27 is EPP2SRAM:M0|epp_state~669 at LCCOMB_X10_Y7_N20
B1L27 = B1L17 & B1_epp_state.EPP_IDLE & B1_epp_state.EPP_WAIT_ADDRWRITE # !B1_epp_state.EPP_IDLE & !B1_EPP_Write;


--B1L37 is EPP2SRAM:M0|epp_state~670 at LCCOMB_X10_Y7_N6
B1L37 = B1L17 & B1_epp_state.EPP_IDLE & B1_epp_state.EPP_WAIT_ADDRREAD # !B1_epp_state.EPP_IDLE & B1_EPP_Write;


--B1L47 is EPP2SRAM:M0|epp_state~671 at LCCOMB_X10_Y7_N26
B1L47 = B1_EPP_AddressStrobe & !B1_EPP_DataStrobe;


--B1L57 is EPP2SRAM:M0|epp_state~672 at LCCOMB_X10_Y7_N22
B1L57 = RST & B1_epp_state.EPP_IDLE & B1L07 # !B1_epp_state.EPP_IDLE & B1L47;


--B1L67 is EPP2SRAM:M0|epp_state~673 at LCCOMB_X10_Y7_N14
B1L67 = B1L57 & B1_epp_state.EPP_IDLE & B1_epp_state.EPP_WAIT_DATAWRITE # !B1_epp_state.EPP_IDLE & !B1_EPP_Write;


--B1L77 is EPP2SRAM:M0|epp_state~674 at LCCOMB_X10_Y7_N12
B1L77 = B1L57 & B1_epp_state.EPP_IDLE & B1_epp_state.EPP_WAIT_DATAREAD # !B1_epp_state.EPP_IDLE & B1_EPP_Write;


--B1L5 is EPP2SRAM:M0|EPP_Data~26 at LCCOMB_X10_Y6_N10
B1L5 = B1_epp_state.EPP_WAIT_DATAREAD # B1_epp_state.EPP_WAIT_ADDRREAD;


--B1L87 is EPP2SRAM:M0|epp_state~675 at LCCOMB_X10_Y6_N14
B1L87 = B1L5 # B1L96 # B1_epp_state.EPP_WAIT_DATAWRITE # B1_epp_state.EPP_WAIT_ADDRWRITE;


--B1L97 is EPP2SRAM:M0|epp_state~676 at LCCOMB_X10_Y7_N28
B1L97 = RST & B1L07 & B1_epp_state.EPP_IDLE # !B1L87;


--B1_epp_dataout[7] is EPP2SRAM:M0|epp_dataout[7] at LCFF_X10_Y6_N31
B1_epp_dataout[7] = DFFEAS(B1L95, GLOBAL(A1L11),  ,  , B1L85,  ,  ,  ,  );


--B1_epp_dataout[6] is EPP2SRAM:M0|epp_dataout[6] at LCFF_X10_Y6_N1
B1_epp_dataout[6] = DFFEAS(B1L06, GLOBAL(A1L11),  ,  , B1L85,  ,  ,  ,  );


--B1_epp_dataout[5] is EPP2SRAM:M0|epp_dataout[5] at LCFF_X10_Y6_N7
B1_epp_dataout[5] = DFFEAS(B1L16, GLOBAL(A1L11),  ,  , B1L85,  ,  ,  ,  );


--B1_epp_dataout[4] is EPP2SRAM:M0|epp_dataout[4] at LCFF_X10_Y6_N25
B1_epp_dataout[4] = DFFEAS(B1L26, GLOBAL(A1L11),  ,  , B1L85,  ,  ,  ,  );


--B1_epp_dataout[3] is EPP2SRAM:M0|epp_dataout[3] at LCFF_X10_Y6_N23
B1_epp_dataout[3] = DFFEAS(B1L36, GLOBAL(A1L11),  ,  , B1L85,  ,  ,  ,  );


--B1_epp_dataout[2] is EPP2SRAM:M0|epp_dataout[2] at LCFF_X10_Y6_N9
B1_epp_dataout[2] = DFFEAS(B1L25, GLOBAL(A1L11),  ,  , B1L85,  ,  , !RST,  );


--B1_epp_dataout[1] is EPP2SRAM:M0|epp_dataout[1] at LCFF_X10_Y6_N5
B1_epp_dataout[1] = DFFEAS(B1L05, GLOBAL(A1L11),  ,  , B1L85,  ,  , !RST,  );


--B1_epp_dataout[0] is EPP2SRAM:M0|epp_dataout[0] at LCFF_X10_Y6_N21
B1_epp_dataout[0] = DFFEAS(B1L84, GLOBAL(A1L11),  ,  , B1L85,  ,  , !RST,  );


--C1_data_1_out[7] is ram_dp_ar_aw:m1|data_1_out[7] at LCFF_X6_Y5_N23
C1_data_1_out[7] = DFFEAS(C1L901, GLOBAL(A1L11),  ,  ,  ,  ,  ,  ,  );


--C1L3Q is ram_dp_ar_aw:m1|always1~2 at LCFF_X8_Y6_N23
C1L3Q = DFFEAS(C1L4, GLOBAL(A1L11),  ,  ,  ,  ,  ,  ,  );


--C1L6 is ram_dp_ar_aw:m1|always2~34 at LCCOMB_X7_Y4_N30
C1L6 = C1_data_1_out[7] # !C1L3Q;


--C1L711 is ram_dp_ar_aw:m1|data_1~46 at LCCOMB_X6_Y5_N16
C1L711 = SRAMWE & !SRAMOE & !SRAMCS;


--C1_data_1_out[6] is ram_dp_ar_aw:m1|data_1_out[6] at LCFF_X8_Y5_N15
C1_data_1_out[6] = DFFEAS(C1L011, GLOBAL(A1L11),  ,  ,  ,  ,  ,  ,  );


--C1L7 is ram_dp_ar_aw:m1|always2~35 at LCCOMB_X8_Y5_N2
C1L7 = C1_data_1_out[6] # !C1L3Q;


--C1_data_1_out[5] is ram_dp_ar_aw:m1|data_1_out[5] at LCFF_X7_Y5_N25
C1_data_1_out[5] = DFFEAS(C1L111, GLOBAL(A1L11),  ,  ,  ,  ,  ,  ,  );


--C1L8 is ram_dp_ar_aw:m1|always2~36 at LCCOMB_X7_Y4_N8
C1L8 = C1_data_1_out[5] # !C1L3Q;


--C1_data_1_out[4] is ram_dp_ar_aw:m1|data_1_out[4] at LCFF_X8_Y5_N17
C1_data_1_out[4] = DFFEAS(C1L211, GLOBAL(A1L11),  ,  ,  ,  ,  ,  ,  );


--C1L9 is ram_dp_ar_aw:m1|always2~37 at LCCOMB_X7_Y4_N12
C1L9 = C1_data_1_out[4] # !C1L3Q;


--C1_data_1_out[3] is ram_dp_ar_aw:m1|data_1_out[3] at LCFF_X7_Y5_N17
C1_data_1_out[3] = DFFEAS(C1L311, GLOBAL(A1L11),  ,  ,  ,  ,  ,  ,  );


--C1L01 is ram_dp_ar_aw:m1|always2~38 at LCCOMB_X7_Y4_N10
C1L01 = C1_data_1_out[3] # !C1L3Q;


--C1_data_1_out[2] is ram_dp_ar_aw:m1|data_1_out[2] at LCFF_X6_Y5_N3
C1_data_1_out[2] = DFFEAS(C1L411, GLOBAL(A1L11),  ,  ,  ,  ,  ,  ,  );


--C1L11 is ram_dp_ar_aw:m1|always2~39 at LCCOMB_X6_Y5_N20
C1L11 = C1_data_1_out[2] # !C1L3Q;


--C1_data_1_out[1] is ram_dp_ar_aw:m1|data_1_out[1] at LCFF_X7_Y5_N5
C1_data_1_out[1] = DFFEAS(C1L511, GLOBAL(A1L11),  ,  ,  ,  ,  ,  ,  );


--C1L21 is ram_dp_ar_aw:m1|always2~40 at LCCOMB_X7_Y4_N26
C1L21 = C1_data_1_out[1] # !C1L3Q;


--C1_data_1_out[0] is ram_dp_ar_aw:m1|data_1_out[0] at LCFF_X7_Y5_N13
C1_data_1_out[0] = DFFEAS(C1L611, GLOBAL(A1L11),  ,  ,  ,  ,  ,  ,  );


--C1L31 is ram_dp_ar_aw:m1|always2~41 at LCCOMB_X7_Y4_N22
C1L31 = C1_data_1_out[0] # !C1L3Q;


--B1L8 is EPP2SRAM:M0|EPP_Write~3 at LCCOMB_X8_Y7_N16
B1L8 = WRITE # !RST;


--B1_epp_datain[7] is EPP2SRAM:M0|epp_datain[7] at LCFF_X8_Y7_N29
B1_epp_datain[7] = DFFEAS(B1L83, GLOBAL(A1L11),  ,  , B1L03,  ,  ,  ,  );


--C1_data_0_out[7] is ram_dp_ar_aw:m1|data_0_out[7] at LCFF_X9_Y6_N19
C1_data_0_out[7] = DFFEAS(C1L85, GLOBAL(A1L11),  ,  ,  ,  ,  ,  ,  );


--B1_cmd[0] is EPP2SRAM:M0|cmd[0] at LCFF_X10_Y6_N17
B1_cmd[0] = DFFEAS(B1L72, GLOBAL(A1L11),  ,  ,  ,  ,  , !RST,  );


--A1L8 is ADD_DATA[7]~432 at LCCOMB_X7_Y6_N10
A1L8 = B1_cmd[0] & B1_epp_datain[7] # !B1_cmd[0] & C1_data_0_out[7] # !C1L3Q;


--B1L95 is EPP2SRAM:M0|epp_dataout~519 at LCCOMB_X10_Y6_N30
B1L95 = A1L8 & RST & B1_EPP_AddressStrobe;


--B1L85 is EPP2SRAM:M0|epp_dataout[7]~520 at LCCOMB_X10_Y7_N18
B1L85 = !B1_epp_state.EPP_IDLE & B1_EPP_Write & !B1L96 # !RST;


--B1_epp_datain[6] is EPP2SRAM:M0|epp_datain[6] at LCFF_X8_Y7_N7
B1_epp_datain[6] = DFFEAS(B1L93, GLOBAL(A1L11),  ,  , B1L03,  ,  ,  ,  );


--C1_data_0_out[6] is ram_dp_ar_aw:m1|data_0_out[6] at LCFF_X8_Y5_N19
C1_data_0_out[6] = DFFEAS(C1L95, GLOBAL(A1L11),  ,  ,  ,  ,  ,  ,  );


--A1L7 is ADD_DATA[6]~433 at LCCOMB_X8_Y5_N8
A1L7 = B1_cmd[0] & B1_epp_datain[6] # !B1_cmd[0] & C1_data_0_out[6] # !C1L3Q;


--B1L06 is EPP2SRAM:M0|epp_dataout~521 at LCCOMB_X10_Y6_N0
B1L06 = RST & B1_EPP_AddressStrobe & A1L7;


--B1_epp_datain[5] is EPP2SRAM:M0|epp_datain[5] at LCFF_X8_Y7_N11
B1_epp_datain[5] = DFFEAS(B1L04, GLOBAL(A1L11),  ,  , B1L03,  ,  ,  ,  );


--C1_data_0_out[5] is ram_dp_ar_aw:m1|data_0_out[5] at LCFF_X8_Y6_N15
C1_data_0_out[5] = DFFEAS(C1L06, GLOBAL(A1L11),  ,  ,  ,  ,  ,  ,  );


--A1L6 is ADD_DATA[5]~434 at LCCOMB_X7_Y4_N18
A1L6 = B1_cmd[0] & B1_epp_datain[5] # !B1_cmd[0] & C1_data_0_out[5] # !C1L3Q;


--B1L16 is EPP2SRAM:M0|epp_dataout~522 at LCCOMB_X10_Y6_N6
B1L16 = RST & B1_EPP_AddressStrobe & A1L6;


--B1_epp_datain[4] is EPP2SRAM:M0|epp_datain[4] at LCFF_X8_Y7_N9
B1_epp_datain[4] = DFFEAS(B1L14, GLOBAL(A1L11),  ,  , B1L03,  ,  ,  ,  );


--C1_data_0_out[4] is ram_dp_ar_aw:m1|data_0_out[4] at LCFF_X8_Y5_N21
C1_data_0_out[4] = DFFEAS(C1L16, GLOBAL(A1L11),  ,  ,  ,  ,  ,  ,  );


--A1L5 is ADD_DATA[4]~435 at LCCOMB_X8_Y5_N4
A1L5 = B1_cmd[0] & B1_epp_datain[4] # !B1_cmd[0] & C1_data_0_out[4] # !C1L3Q;


--B1L26 is EPP2SRAM:M0|epp_dataout~523 at LCCOMB_X10_Y6_N24
B1L26 = A1L5 & B1_EPP_AddressStrobe & RST;


--B1_epp_datain[3] is EPP2SRAM:M0|epp_datain[3] at LCFF_X8_Y7_N23
B1_epp_datain[3] = DFFEAS(B1L24, GLOBAL(A1L11),  ,  , B1L03,  ,  ,  ,  );


--C1_data_0_out[3] is ram_dp_ar_aw:m1|data_0_out[3] at LCFF_X8_Y5_N1
C1_data_0_out[3] = DFFEAS(C1L26, GLOBAL(A1L11),  ,  ,  ,  ,  ,  ,  );


--A1L4 is ADD_DATA[3]~436 at LCCOMB_X8_Y6_N16
A1L4 = B1_cmd[0] & B1_epp_datain[3] # !B1_cmd[0] & C1_data_0_out[3] # !C1L3Q;


--B1L36 is EPP2SRAM:M0|epp_dataout~524 at LCCOMB_X10_Y6_N22
B1L36 = A1L4 & B1_EPP_AddressStrobe & RST;


--B1_epp_datain[2] is EPP2SRAM:M0|epp_datain[2] at LCFF_X8_Y7_N27
B1_epp_datain[2] = DFFEAS(B1L34, GLOBAL(A1L11),  ,  , B1L03,  ,  ,  ,  );


--C1_data_0_out[2] is ram_dp_ar_aw:m1|data_0_out[2] at LCFF_X6_Y5_N11
C1_data_0_out[2] = DFFEAS(C1L36, GLOBAL(A1L11),  ,  ,  ,  ,  ,  ,  );


--A1L3 is ADD_DATA[2]~437 at LCCOMB_X6_Y5_N28
A1L3 = B1_cmd[0] & B1_epp_datain[2] # !B1_cmd[0] & C1_data_0_out[2] # !C1L3Q;


--B1_sram_waddr[2] is EPP2SRAM:M0|sram_waddr[2] at LCFF_X9_Y5_N27
B1_sram_waddr[2] = DFFEAS(B1L32, GLOBAL(A1L11),  ,  , B1L78,  ,  , !RST,  );


--B1_sram_raddr[2] is EPP2SRAM:M0|sram_raddr[2] at LCFF_X9_Y5_N23
B1_sram_raddr[2] = DFFEAS(B1L02, GLOBAL(A1L11),  ,  , B1L28,  ,  , !RST,  );


--B1L11 is EPP2SRAM:M0|SRAM_ADDR[2]~125 at LCCOMB_X9_Y6_N30
B1L11 = B1_cmd[0] & B1_sram_waddr[2] # !B1_cmd[0] & B1_sram_raddr[2];


--B1L25 is EPP2SRAM:M0|epp_dataout[2]~525 at LCCOMB_X10_Y6_N8
B1L25 = B1_EPP_AddressStrobe & A1L3 # !B1_EPP_AddressStrobe & B1L11;


--B1_epp_datain[1] is EPP2SRAM:M0|epp_datain[1] at LCFF_X8_Y7_N13
B1_epp_datain[1] = DFFEAS(B1L44, GLOBAL(A1L11),  ,  , B1L03,  ,  ,  ,  );


--C1_data_0_out[1] is ram_dp_ar_aw:m1|data_0_out[1] at LCFF_X6_Y5_N19
C1_data_0_out[1] = DFFEAS(C1L46, GLOBAL(A1L11),  ,  ,  ,  ,  ,  ,  );


--A1L2 is ADD_DATA[1]~438 at LCCOMB_X6_Y5_N14
A1L2 = B1_cmd[0] & B1_epp_datain[1] # !B1_cmd[0] & C1_data_0_out[1] # !C1L3Q;


--B1_sram_waddr[1] is EPP2SRAM:M0|sram_waddr[1] at LCFF_X9_Y5_N7
B1_sram_waddr[1] = DFFEAS(B1L22, GLOBAL(A1L11),  ,  , B1L78,  ,  , !RST,  );


--B1_sram_raddr[1] is EPP2SRAM:M0|sram_raddr[1] at LCFF_X9_Y5_N11
B1_sram_raddr[1] = DFFEAS(B1L91, GLOBAL(A1L11),  ,  , B1L28,  ,  , !RST,  );


--B1L01 is EPP2SRAM:M0|SRAM_ADDR[1]~126 at LCCOMB_X9_Y6_N0
B1L01 = B1_cmd[0] & B1_sram_waddr[1] # !B1_cmd[0] & B1_sram_raddr[1];


--B1L05 is EPP2SRAM:M0|epp_dataout[1]~526 at LCCOMB_X10_Y6_N4
B1L05 = B1_EPP_AddressStrobe & A1L2 # !B1_EPP_AddressStrobe & B1L01;


--B1_epp_datain[0] is EPP2SRAM:M0|epp_datain[0] at LCFF_X8_Y7_N31
B1_epp_datain[0] = DFFEAS(B1L54, GLOBAL(A1L11),  ,  , B1L03,  ,  ,  ,  );


--C1_data_0_out[0] is ram_dp_ar_aw:m1|data_0_out[0] at LCFF_X6_Y5_N31
C1_data_0_out[0] = DFFEAS(C1L56, GLOBAL(A1L11),  ,  ,  ,  ,  ,  ,  );


--A1L1 is ADD_DATA[0]~439 at LCCOMB_X6_Y5_N8
A1L1 = B1_cmd[0] & B1_epp_datain[0] # !B1_cmd[0] & C1_data_0_out[0] # !C1L3Q;


--B1_sram_waddr[0] is EPP2SRAM:M0|sram_waddr[0] at LCFF_X9_Y5_N3
B1_sram_waddr[0] = DFFEAS(B1L12, GLOBAL(A1L11),  ,  , B1L78,  ,  , !RST,  );


--B1_sram_raddr[0] is EPP2SRAM:M0|sram_raddr[0] at LCFF_X9_Y5_N1
B1_sram_raddr[0] = DFFEAS(B1L81, GLOBAL(A1L11),  ,  , B1L28,  ,  , !RST,  );


--B1L9 is EPP2SRAM:M0|SRAM_ADDR[0]~127 at LCCOMB_X9_Y6_N22
B1L9 = B1_cmd[0] & B1_sram_waddr[0] # !B1_cmd[0] & B1_sram_raddr[0];


--B1L84 is EPP2SRAM:M0|epp_dataout[0]~527 at LCCOMB_X10_Y6_N20
B1L84 = B1_EPP_AddressStrobe & A1L1 # !B1_EPP_AddressStrobe & B1L9;


--C1_mem[5][7] is ram_dp_ar_aw:m1|mem[5][7] at LCFF_X7_Y5_N27
C1_mem[5][7] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11),  ,  , C1L981, C1L031,  ,  , VCC);


--C1L37 is ram_dp_ar_aw:m1|data_1_out[0]~293 at LCCOMB_X5_Y6_N14
C1L37 = SRAMADDR[0] & SRAMADDR[1] # SRAMADDR[2];


--C1_mem[2][7] is ram_dp_ar_aw:m1|mem[2][7] at LCFF_X6_Y6_N13
C1_mem[2][7] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11),  ,  , C1L751, C1L031,  ,  , VCC);


--C1_mem[4][7] is ram_dp_ar_aw:m1|mem[4][7] at LCFF_X5_Y6_N23
C1_mem[4][7] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11),  ,  , C1L871, C1L031,  ,  , VCC);


--C1_mem[0][7] is ram_dp_ar_aw:m1|mem[0][7] at LCFF_X6_Y6_N15
C1_mem[0][7] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11),  ,  , C1L721, C1L031,  ,  , VCC);


--C1L501 is ram_dp_ar_aw:m1|data_1_out[7]~117 at LCCOMB_X5_Y6_N22
C1L501 = SRAMADDR[1] & SRAMADDR[2] # !SRAMADDR[1] & SRAMADDR[2] & C1_mem[4][7] # !SRAMADDR[2] & C1_mem[0][7];


--C1_mem[6][7] is ram_dp_ar_aw:m1|mem[6][7] at LCFF_X7_Y6_N17
C1_mem[6][7] = DFFEAS(C1L031, GLOBAL(A1L11),  ,  , C1L602,  ,  ,  ,  );


--C1L601 is ram_dp_ar_aw:m1|data_1_out[7]~118 at LCCOMB_X6_Y6_N12
C1L601 = SRAMADDR[1] & C1L501 & C1_mem[6][7] # !C1L501 & C1_mem[2][7] # !SRAMADDR[1] & C1L501;


--C1L86 is ram_dp_ar_aw:m1|data_1_out[0]~108 at LCCOMB_X5_Y6_N28
C1L86 = SRAMADDR[1] # !SRAMADDR[0];


--C1_mem[1][7] is ram_dp_ar_aw:m1|mem[1][7] at LCFF_X7_Y6_N31
C1_mem[1][7] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11),  ,  , C1L241, C1L031,  ,  , VCC);


--C1L701 is ram_dp_ar_aw:m1|data_1_out[7]~119 at LCCOMB_X7_Y6_N30
C1L701 = C1L37 & C1L86 # !C1L37 & C1L86 & C1L601 # !C1L86 & C1_mem[1][7];


--C1_mem[3][7] is ram_dp_ar_aw:m1|mem[3][7] at LCFF_X9_Y6_N17
C1_mem[3][7] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11),  ,  , C1L661, C1L031,  ,  , VCC);


--C1L801 is ram_dp_ar_aw:m1|data_1_out[7]~120 at LCCOMB_X7_Y5_N26
C1L801 = C1L37 & C1L701 & C1_mem[3][7] # !C1L701 & C1_mem[5][7] # !C1L37 & C1L701;


--C1L901 is ram_dp_ar_aw:m1|data_1_out~109 at LCCOMB_X6_Y5_N22
C1L901 = SRAMWE & !SRAMOE & C1L801 & !SRAMCS;


--C1L5 is ram_dp_ar_aw:m1|always1~178 at LCCOMB_X8_Y6_N2
C1L5 = RST & !B1_EPP_Wait;


--C1L4 is ram_dp_ar_aw:m1|always1~27 at LCCOMB_X8_Y6_N22
C1L4 = AS & WRITE & DS & C1L5;


--C1_mem[4][6] is ram_dp_ar_aw:m1|mem[4][6] at LCFF_X6_Y4_N11
C1_mem[4][6] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11),  ,  , C1L871, C1L131,  ,  , VCC);


--C1_mem[2][6] is ram_dp_ar_aw:m1|mem[2][6] at LCFF_X6_Y6_N17
C1_mem[2][6] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11),  ,  , C1L751, C1L131,  ,  , VCC);


--C1_mem[0][6] is ram_dp_ar_aw:m1|mem[0][6] at LCFF_X6_Y6_N31
C1_mem[0][6] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11),  ,  , C1L721, C1L131,  ,  , VCC);


--C1L001 is ram_dp_ar_aw:m1|data_1_out[6]~121 at LCCOMB_X6_Y6_N16
C1L001 = SRAMADDR[1] & SRAMADDR[2] # C1_mem[2][6] # !SRAMADDR[1] & !SRAMADDR[2] & C1_mem[0][6];


--C1_mem[6][6] is ram_dp_ar_aw:m1|mem[6][6] at LCFF_X7_Y6_N29
C1_mem[6][6] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11),  ,  , C1L602, C1L131,  ,  , VCC);


--C1L101 is ram_dp_ar_aw:m1|data_1_out[6]~122 at LCCOMB_X6_Y4_N10
C1L101 = SRAMADDR[2] & C1L001 & C1_mem[6][6] # !C1L001 & C1_mem[4][6] # !SRAMADDR[2] & C1L001;


--C1_mem[5][6] is ram_dp_ar_aw:m1|mem[5][6] at LCFF_X7_Y5_N1
C1_mem[5][6] = DFFEAS(UNCONNECTED_DATAIN, GLOBAL(A1L11),  ,  , C1L981, C1L131,  ,  , VCC);


--C1_mem[1][6] is ram_dp_ar_aw:m1|mem[1][6] at LCFF_X7_Y6_N25