epptop.v

在altera fpga中实现epp模式的并口通信程序

module EPPTOP
(
WRITE,//a7
INT,//a11
WAIT,//a12
DS,//a8
RST,//a9
AS,//a10
CLK,
EPPDATA,//c8~c14 D8

SRAMADDR,//E11 E10 K11
SRAMDATA,//D9 B8 K10 G9 H10 J10 D10 B10
SRAMCS,//G11
SRAMWE,//G10
SRAMOE);//D11

input WRITE;
input DS;
input RST;
input AS;
input CLK;
input [2:0]SRAMADDR;
input SRAMCS;
input SRAMWE;
input SRAMOE;
output INT;
output WAIT;
inout [7:0]EPPDATA;
inout [7:0]SRAMDATA;

wire ADD_CE;
wire ADD_OE;
wire ADD_WE;
wire [2:0]ADD_ADDR;
wire [7:0]ADD_DATA;
wire ADD_ENV;

wire WRITE;
wire DS;
wire RST;
wire AS;
wire CLK;
wire [2:0]SRAMADDR;
wire SRAMCS;
wire SRAMWE;
wire SRAMOE;
wire INT;
wire WAIT;
wire [7:0]EPPDATA;
wire [7:0]SRAMDATA;


  
	
EPP2SRAM M0(.EPP_Write0(WRITE),.EPP_Data(EPPDATA),.EPP_Interrupt(INT),.EPP_Wait(WAIT),
.EPP_DataStrobe0(DS),.EPP_Reset0(RST),.EPP_AddressStrobe0(AS),
.clk(CLK),.SRAM_CE(ADD_CE),.SRAM_OE(ADD_OE),.SRAM_WE(ADD_WE),.SRAM_ADDR(ADD_ADDR),.SRAM_DATA(ADD_DATA),.ENV(ADD_ENV));



ram_dp_ar_aw m1(.address_1(SRAMADDR),.cs_1(SRAMCS),.we_1(SRAMWE),.oe_1(SRAMOE),
.sclk(CLK),.RESET(RST),
.data_1(SRAMDATA),.cs_0(ADD_CE),.oe_0(ADD_OE),.we_0(ADD_WE),.address_0(ADD_ADDR),.data_0(ADD_DATA),.SENV(ADD_ENV));



endmodule