epptop.map.smsg

在altera fpga中实现epp模式的并口通信程序

Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Tue Dec 30 21:43:03 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off EPPTOP -c EPPTOP
Info: Found 1 design units, including 1 entities, in source file EPP2SRAM.v
    Info: Found entity 1: EPP2SRAM
Info: Found 1 design units, including 1 entities, in source file ram_dp_ar_aw.v
    Info: Found entity 1: ram_dp_ar_aw
Info: Found 1 design units, including 1 entities, in source file EPPTOP.v
    Info: Found entity 1: EPPTOP
Info: Elaborating entity "EPPTOP" for the top level hierarchy
Info: Elaborating entity "EPP2SRAM" for hierarchy "EPP2SRAM:M0"
Warning (10036): Verilog HDL or VHDL warning at EPP2SRAM.v(71): object "EPP_Reset" assigned a value but never read
Info: Elaborating entity "ram_dp_ar_aw" for hierarchy "ram_dp_ar_aw:m1"
Warning: Reduced register "EPP2SRAM:M0|EPP_Interrupt" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "ram_dp_ar_aw:m1|always1~4" merged to single register "ram_dp_ar_aw:m1|always1~2"
    Info: Duplicate register "ram_dp_ar_aw:m1|always1~5" merged to single register "ram_dp_ar_aw:m1|always1~2"
    Info: Duplicate register "ram_dp_ar_aw:m1|always1~6" merged to single register "ram_dp_ar_aw:m1|always1~2"
    Info: Duplicate register "ram_dp_ar_aw:m1|always1~7" merged to single register "ram_dp_ar_aw:m1|always1~2"
    Info: Duplicate register "ram_dp_ar_aw:m1|always1~8" merged to single register "ram_dp_ar_aw:m1|always1~2"
    Info: Duplicate register "ram_dp_ar_aw:m1|always1~9" merged to single register "ram_dp_ar_aw:m1|always1~2"
    Info: Duplicate register "ram_dp_ar_aw:m1|always1~10" merged to single register "ram_dp_ar_aw:m1|always1~2"
    Info: Duplicate register "ram_dp_ar_aw:m1|always2~2" merged to single register "ram_dp_ar_aw:m1|always1~2"
    Info: Duplicate register "ram_dp_ar_aw:m1|always2~3" merged to single register "ram_dp_ar_aw:m1|always1~2"
    Info: Duplicate register "ram_dp_ar_aw:m1|always2~4" merged to single register "ram_dp_ar_aw:m1|always1~2"
    Info: Duplicate register "ram_dp_ar_aw:m1|always2~5" merged to single register "ram_dp_ar_aw:m1|always1~2"
    Info: Duplicate register "ram_dp_ar_aw:m1|always2~6" merged to single register "ram_dp_ar_aw:m1|always1~2"
    Info: Duplicate register "ram_dp_ar_aw:m1|always2~7" merged to single register "ram_dp_ar_aw:m1|always1~2"
    Info: Duplicate register "ram_dp_ar_aw:m1|always2~8" merged to single register "ram_dp_ar_aw:m1|always1~2"
    Info: Duplicate register "ram_dp_ar_aw:m1|always2~9" merged to single register "ram_dp_ar_aw:m1|always1~2"
Info: State machine "|EPPTOP|EPP2SRAM:M0|epp_state" contains 5 states
Info: Selected Auto state machine encoding method for state machine "|EPPTOP|EPP2SRAM:M0|epp_state"
Info: Encoding result for state machine "|EPPTOP|EPP2SRAM:M0|epp_state"
    Info: Completed encoding using 5 state bits
        Info: Encoded state bit "EPP2SRAM:M0|epp_state.EPP_WAIT_ADDRREAD"
        Info: Encoded state bit "EPP2SRAM:M0|epp_state.EPP_WAIT_ADDRWRITE"
        Info: Encoded state bit "EPP2SRAM:M0|epp_state.EPP_WAIT_DATAREAD"
        Info: Encoded state bit "EPP2SRAM:M0|epp_state.EPP_IDLE"
        Info: Encoded state bit "EPP2SRAM:M0|epp_state.EPP_WAIT_DATAWRITE"
    Info: State "|EPPTOP|EPP2SRAM:M0|epp_state.EPP_IDLE" uses code string "00000"
    Info: State "|EPPTOP|EPP2SRAM:M0|epp_state.EPP_WAIT_DATAREAD" uses code string "00110"
    Info: State "|EPPTOP|EPP2SRAM:M0|epp_state.EPP_WAIT_ADDRWRITE" uses code string "01010"
    Info: State "|EPPTOP|EPP2SRAM:M0|epp_state.EPP_WAIT_ADDRREAD" uses code string "10010"
    Info: State "|EPPTOP|EPP2SRAM:M0|epp_state.EPP_WAIT_DATAWRITE" uses code string "00011"
Warning: Converting TRI node "ram_dp_ar_aw:m1|data_0~26" that feeds logic to an OR gate
Warning: Converting TRI node "ram_dp_ar_aw:m1|data_0~30" that feeds logic to an OR gate
Warning: Converting TRI node "ram_dp_ar_aw:m1|data_0~34" that feeds logic to an OR gate
Warning: Converting TRI node "ram_dp_ar_aw:m1|data_0~38" that feeds logic to an OR gate
Warning: Converting TRI node "ram_dp_ar_aw:m1|data_0~42" that feeds logic to an OR gate
Warning: Converting TRI node "ram_dp_ar_aw:m1|data_0~46" that feeds logic to an OR gate
Warning: Converting TRI node "ram_dp_ar_aw:m1|data_0~50" that feeds logic to an OR gate
Warning: Converting TRI node "ram_dp_ar_aw:m1|data_0~54" that feeds logic to an OR gate
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "INT" stuck at GND
Info: 2 registers lost all their fanouts during netlist optimizations. The first 2 are displayed below.
    Info: Register "M0/epp_state~119" lost all its fanouts during netlist optimizations.
    Info: Register "M0/epp_state~120" lost all its fanouts during netlist optimizations.
Info: Implemented 212 device resources after synthesis - the final resource count might be different
    Info: Implemented 11 input pins
    Info: Implemented 2 output pins
    Info: Implemented 16 bidirectional pins
    Info: Implemented 183 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings
    Info: Allocated 132 megabytes of memory during processing
    Info: Processing ended: Tue Dec 30 21:43:07 2008
    Info: Elapsed time: 00:00:04