ram_dp_ar_aw.v

在altera fpga中实现epp模式的并口通信程序

module ram_dp_ar_aw 
(
address_0 , // address_0 Input
data_0    , // data_0 bi-directional
cs_0      , // Chip Select
we_0      , // Write Enable/Read Enable
oe_0      , // Output Enable
address_1 , // address_1 Input
data_1    , // data_1 bi-directional
cs_1      , // Chip Select
we_1      , // Write Enable/Read Enable
oe_1,       // Output Enable
sclk,
SENV,
RESET
); 

//--------------Input Ports----------------------- 
input [2:0] address_0 ;
input cs_0 ;
input we_0 ;
input oe_0 ; 
input [2:0] address_1 ;
input cs_1 ;
input we_1 ;
input oe_1 ;
input sclk;           
input SENV; 
input RESET;
//--------------Inout Ports-----------------------
inout [7:0] data_0 ; 
inout [7:0] data_1 ;
//--------------Output Ports-----------------------


//--------------Internal variables---------------- 
reg [7:0] data_0_out ; 
reg [7:0] data_1_out ;
reg [7:0] mem [0:6];

//--------------Code Starts Here------------------ 
// Memory Write Block 
// Write Operation : When we_0 = 0, cs_0 = 0,oe_0=1

always @ (posedge sclk)
begin
    if(!RESET)
	   begin
	      mem[0]<=8'b00000000;
	      mem[1]<=8'b00000000;
	      mem[2]<=8'b00000000;
	      mem[3]<=8'b00000000;
	      mem[4]<=8'b00000000;
	      mem[5]<=8'b00000000;
	      mem[6]<=8'b00000000;
	   end
	else
	   begin
	      if(SENV)
	         begin
	            if(!cs_0&&!we_0&&oe_0)
	                begin
	                   mem[address_0] <= data_0;
	                end
	            else if(!cs_1&&!we_1&&oe_1)
	                begin
	                   mem[address_1] <= data_1;
	                end
	         end
	      else
	         begin
	             mem[0]<=8'b00000000;
	             mem[1]<=8'b00000000;
	             mem[2]<=8'b00000000;
	             mem[3]<=8'b00000000;
	             mem[4]<=8'b00000000;
	             mem[5]<=8'b00000000;
	             mem[6]<=8'b00000000;
	         end
	   end
end

/*always @ (address_0 or cs_0 or we_0 or data_0 or address_1 or cs_1 or we_1 or data_1)
begin //: MEM_WRITE
  if ( !cs_0 && !we_0 ) 
     begin
       mem[address_0] <= data_0;
     end 
  else if  (!cs_1 && !we_1) 
     begin
       mem[address_1] <= data_1;
     end
end*/

// Memory Read Block 
// Read Operation : When we_0 = 1, oe_0 = 0, cs_0 = 0
always @ (posedge sclk)
begin
    if(!RESET)
	   begin
	      data_0_out <=8'bz;
	   end
	else
	   begin
	      if(SENV)
	         begin
	            if(!cs_0&&we_0&&!oe_0)
	                begin
	                   data_0_out <= mem[address_0];
	                end
	            else 
	                begin
	                   data_0_out <= 0;
	                end
	         end
	      else
	         begin
	             data_0_out <=8'bz;
	         end
	   end
end

/*always @ (address_0 or cs_0 or we_0 or oe_0)
begin //: MEM_READ_0
  if (!cs_0 && we_0 && !oe_0) 
     begin
        data_0_out <= mem[address_0]; 
     end 
  else 
     begin
        data_0_out <= 0; 
     end
end */

 // Memory Read Block 1 
// Read Operation : When we_1 = 1, oe_1 = 0, cs_1 = 0
always @ (posedge sclk)
begin
    if(!RESET)
	   begin
	      data_1_out <=8'bz;
	   end
	else
	   begin
	      if(SENV)
	         begin
	            if(!cs_1&&we_1&&!oe_1)
	                begin
	                   data_1_out <= mem[address_1];
	                end
	            else 
	                begin
	                   data_1_out <= 0;
	                end
	         end
	      else
	         begin
	             data_1_out <=8'bz;
	         end
	   end
end

/*always @ (address_1 or cs_1 or we_1 or oe_1)
begin //: MEM_READ_1
  if (!cs_1 && we_1 && !oe_1) 
     begin
        data_1_out <= mem[address_1]; 
     end 
  else 
     begin
        data_1_out <= 0; 
     end
end*/

// Tri-State Buffer control 
// output : When we_0 = 1, oe_0 = 0, cs_0 = 0
assign data_0 = (!cs_0 && !oe_0 && we_0) ? data_0_out : 8'bz;
 

// Tri-State Buffer control 
// output : When we_0 = 1, oe_0 = 0, cs_0 = 0
assign data_1 = (!cs_1 && !oe_1 && we_1) ? data_1_out : 8'bz;

endmodule // End of Module ram_dp_ar_aw