epptop.tan.summary

在altera fpga中实现epp模式的并口通信程序

--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------

Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 10.349 ns
From           : SRAMADDR[2]
To             : ram_dp_ar_aw:m1|mem[2][7]
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 8.775 ns
From           : ram_dp_ar_aw:m1|always1~2
To             : SRAMDATA[4]
From Clock     : CLK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 12.980 ns
From           : SRAMWE
To             : SRAMDATA[4]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -3.324 ns
From           : EPPDATA[3]
To             : EPP2SRAM:M0|epp_datain[3]
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : N/A
Required Time  : None
Actual Time    : 222.87 MHz ( period = 4.487 ns )
From           : EPP2SRAM:M0|sram_raddr[2]
To             : ram_dp_ar_aw:m1|data_0_out[0]
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

--------------------------------------------------------------------------------------