epptop.flow.rpt

在altera fpga中实现epp模式的并口通信程序

Flow report for EPPTOP
Tue Dec 30 21:44:41 2008
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Non-Default Global Settings
  5. Flow Elapsed Time
  6. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------+
; Flow Summary                                                             ;
+--------------------------------+-----------------------------------------+
; Flow Status                    ; Successful - Tue Dec 30 21:44:41 2008   ;
; Quartus II Version             ; 7.0 Build 33 02/05/2007 SJ Full Version ;
; Revision Name                  ; EPPTOP                                  ;
; Top-level Entity Name          ; EPPTOP                                  ;
; Family                         ; Stratix II GX                           ;
; Device                         ; EP2SGX30DF780C5                         ;
; Timing Models                  ; Final                                   ;
; Met timing requirements        ; Yes                                     ;
; Logic utilization              ; < 1 %                                   ;
;     Combinational ALUTs        ; 126 / 27,104 ( < 1 % )                  ;
;     Dedicated logic registers  ; 106 / 27,104 ( < 1 % )                  ;
; Total registers                ; 106                                     ;
; Total pins                     ; 29 / 406 ( 7 % )                        ;
; Total virtual pins             ; 0                                       ;
; Total block memory bits        ; 0 / 1,369,728 ( 0 % )                   ;
; DSP block 9-bit elements       ; 0 / 128 ( 0 % )                         ;
; Total GXB Receiver Channels    ; 0 / 8 ( 0 % )                           ;
; Total GXB Transmitter Channels ; 0 / 8 ( 0 % )                           ;
; Total PLLs                     ; 0 / 4 ( 0 % )                           ;
; Total DLLs                     ; 0 / 2 ( 0 % )                           ;
+--------------------------------+-----------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 12/30/2008 21:43:04 ;
; Main task         ; Compilation         ;
; Revision Name     ; EPPTOP              ;
+-------------------+---------------------+


+------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings                                                                                 ;
+-------------------------------+---------------------------------------+---------------+-------------+------------+
; Assignment Name               ; Value                                 ; Default Value ; Entity Name ; Section Id ;
+-------------------------------+---------------------------------------+---------------+-------------+------------+
; MAX_CORE_JUNCTION_TEMP        ; 85                                    ; --            ; --          ; --         ;
; MIN_CORE_JUNCTION_TEMP        ; 0                                     ; --            ; --          ; --         ;
; POWER_BOARD_THERMAL_MODEL     ; None (CONSERVATIVE)                   ; --            ; --          ; --         ;
; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; --            ; --          ; --         ;
; ROUTING_BACK_ANNOTATION_FILE  ; EPPTOP.rcf                            ; --            ; --          ; --         ;
; ROUTING_BACK_ANNOTATION_MODE  ; Normal                                ; --            ; --          ; --         ;
+-------------------------------+---------------------------------------+---------------+-------------+------------+


+----------------------------------------+
; Flow Elapsed Time                      ;
+-------------------------+--------------+
; Module Name             ; Elapsed Time ;
+-------------------------+--------------+
; Analysis & Synthesis    ; 00:00:04     ;
; Fitter                  ; 00:00:48     ;
; Assembler               ; 00:00:23     ;
; Classic Timing Analyzer ; 00:00:01     ;
; Total                   ; 00:01:16     ;
+-------------------------+--------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off EPPTOP -c EPPTOP
quartus_fit --read_settings_files=off --write_settings_files=off EPPTOP -c EPPTOP
quartus_asm --read_settings_files=off --write_settings_files=off EPPTOP -c EPPTOP
quartus_tan --read_settings_files=off --write_settings_files=off EPPTOP -c EPPTOP --timing_analysis_only