📄 epptop.map.rpt
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; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+-------------------------+
; |EPPTOP ; 126 (0) ; 106 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 29 ; 0 ; |EPPTOP ;
; |EPP2SRAM:M0| ; 49 (49) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |EPPTOP|EPP2SRAM:M0 ;
; |ram_dp_ar_aw:m1| ; 77 (77) ; 73 (73) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |EPPTOP|ram_dp_ar_aw:m1 ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+-------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
Encoding Type: One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |EPPTOP|EPP2SRAM:M0|epp_state ;
+------------------------------+-----------------------------+------------------------------+-----------------------------+--------------------+------------------------------+
; Name ; epp_state.EPP_WAIT_ADDRREAD ; epp_state.EPP_WAIT_ADDRWRITE ; epp_state.EPP_WAIT_DATAREAD ; epp_state.EPP_IDLE ; epp_state.EPP_WAIT_DATAWRITE ;
+------------------------------+-----------------------------+------------------------------+-----------------------------+--------------------+------------------------------+
; epp_state.EPP_IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ;
; epp_state.EPP_WAIT_DATAREAD ; 0 ; 0 ; 1 ; 1 ; 0 ;
; epp_state.EPP_WAIT_ADDRWRITE ; 0 ; 1 ; 0 ; 1 ; 0 ;
; epp_state.EPP_WAIT_ADDRREAD ; 1 ; 0 ; 0 ; 1 ; 0 ;
; epp_state.EPP_WAIT_DATAWRITE ; 0 ; 0 ; 0 ; 1 ; 1 ;
+------------------------------+-----------------------------+------------------------------+-----------------------------+--------------------+------------------------------+
+---------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+----------------------------------------+----------------------------------------+
; Register name ; Reason for Removal ;
+----------------------------------------+----------------------------------------+
; M0/EPP_Interrupt ; Stuck at GND due to stuck port data_in ;
; m1/always1~4 ; Merged with m1/always1~2 ;
; m1/always1~5 ; Merged with m1/always1~2 ;
; m1/always1~6 ; Merged with m1/always1~2 ;
; m1/always1~7 ; Merged with m1/always1~2 ;
; m1/always1~8 ; Merged with m1/always1~2 ;
; m1/always1~9 ; Merged with m1/always1~2 ;
; m1/always1~10 ; Merged with m1/always1~2 ;
; m1/always2~2 ; Merged with m1/always1~2 ;
; m1/always2~3 ; Merged with m1/always1~2 ;
; m1/always2~4 ; Merged with m1/always1~2 ;
; m1/always2~5 ; Merged with m1/always1~2 ;
; m1/always2~6 ; Merged with m1/always1~2 ;
; m1/always2~7 ; Merged with m1/always1~2 ;
; m1/always2~8 ; Merged with m1/always1~2 ;
; m1/always2~9 ; Merged with m1/always1~2 ;
; M0/epp_state~119 ; Lost fanout ;
; M0/epp_state~120 ; Lost fanout ;
; Total Number of Removed Registers = 18 ; ;
+----------------------------------------+----------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 106 ;
; Number of registers using Synchronous Clear ; 64 ;
; Number of registers using Synchronous Load ; 56 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 75 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------+
; 3:1 ; 3 bits ; 6 ALUTs ; 3 ALUTs ; 3 ALUTs ; Yes ; |EPPTOP|EPP2SRAM:M0|sram_raddr[2] ;
; 3:1 ; 3 bits ; 6 ALUTs ; 3 ALUTs ; 3 ALUTs ; Yes ; |EPPTOP|EPP2SRAM:M0|sram_waddr[2] ;
; 7:1 ; 8 bits ; 32 ALUTs ; 0 ALUTs ; 32 ALUTs ; Yes ; |EPPTOP|ram_dp_ar_aw:m1|mem[6][2] ;
; 7:1 ; 8 bits ; 32 ALUTs ; 0 ALUTs ; 32 ALUTs ; Yes ; |EPPTOP|ram_dp_ar_aw:m1|mem[5][4] ;
; 7:1 ; 8 bits ; 32 ALUTs ; 0 ALUTs ; 32 ALUTs ; Yes ; |EPPTOP|ram_dp_ar_aw:m1|mem[4][4] ;
; 7:1 ; 8 bits ; 32 ALUTs ; 0 ALUTs ; 32 ALUTs ; Yes ; |EPPTOP|ram_dp_ar_aw:m1|mem[3][4] ;
; 7:1 ; 8 bits ; 32 ALUTs ; 0 ALUTs ; 32 ALUTs ; Yes ; |EPPTOP|ram_dp_ar_aw:m1|mem[2][4] ;
; 7:1 ; 8 bits ; 32 ALUTs ; 0 ALUTs ; 32 ALUTs ; Yes ; |EPPTOP|ram_dp_ar_aw:m1|mem[1][2] ;
; 7:1 ; 8 bits ; 32 ALUTs ; 0 ALUTs ; 32 ALUTs ; Yes ; |EPPTOP|ram_dp_ar_aw:m1|mem[0][6] ;
; 8:1 ; 8 bits ; 40 ALUTs ; 40 ALUTs ; 0 ALUTs ; Yes ; |EPPTOP|ram_dp_ar_aw:m1|data_0_out[0] ;
; 8:1 ; 8 bits ; 40 ALUTs ; 40 ALUTs ; 0 ALUTs ; Yes ; |EPPTOP|ram_dp_ar_aw:m1|data_1_out[6] ;
; 6:1 ; 8 bits ; 32 ALUTs ; 16 ALUTs ; 16 ALUTs ; Yes ; |EPPTOP|EPP2SRAM:M0|epp_datain[5] ;
; 7:1 ; 5 bits ; 20 ALUTs ; 10 ALUTs ; 10 ALUTs ; Yes ; |EPPTOP|EPP2SRAM:M0|epp_dataout[7] ;
; 7:1 ; 3 bits ; 12 ALUTs ; 6 ALUTs ; 6 ALUTs ; Yes ; |EPPTOP|EPP2SRAM:M0|epp_dataout[2] ;
; 7:1 ; 2 bits ; 8 ALUTs ; 6 ALUTs ; 2 ALUTs ; No ; |EPPTOP|EPP2SRAM:M0|epp_state~20 ;
; 8:1 ; 2 bits ; 10 ALUTs ; 8 ALUTs ; 2 ALUTs ; No ; |EPPTOP|EPP2SRAM:M0|epp_state~17 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------+
+----------------------------------------------------------+
; Parameter Settings for User Entity Instance: EPP2SRAM:M0 ;
+--------------------+-------+-----------------------------+
; Parameter Name ; Value ; Type ;
+--------------------+-------+-----------------------------+
; EPP_IDLE ; 000 ; Unsigned Binary ;
; EPP_WAIT_ADDRREAD ; 001 ; Unsigned Binary ;
; EPP_WAIT_ADDRWRITE ; 010 ; Unsigned Binary ;
; EPP_WAIT_DATAREAD ; 011 ; Unsigned Binary ;
; EPP_WAIT_DATAWRITE ; 100 ; Unsigned Binary ;
+--------------------+-------+-----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Tue Dec 30 21:43:03 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off EPPTOP -c EPPTOP
Info: Found 1 design units, including 1 entities, in source file EPP2SRAM.v
Info: Found entity 1: EPP2SRAM
Info: Found 1 design units, including 1 entities, in source file ram_dp_ar_aw.v
Info: Found entity 1: ram_dp_ar_aw
Info: Found 1 design units, including 1 entities, in source file EPPTOP.v
Info: Found entity 1: EPPTOP
Info: Elaborating entity "EPPTOP" for the top level hierarchy
Info: Elaborating entity "EPP2SRAM" for hierarchy "EPP2SRAM:M0"
Warning (10036): Verilog HDL or VHDL warning at EPP2SRAM.v(71): object "EPP_Reset" assigned a value but never read
Info: Elaborating entity "ram_dp_ar_aw" for hierarchy "ram_dp_ar_aw:m1"
Warning: Reduced register "EPP2SRAM:M0|EPP_Interrupt" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
Info: Duplicate register "ram_dp_ar_aw:m1|always1~4" merged to single register "ram_dp_ar_aw:m1|always1~2"
Info: Duplicate register "ram_dp_ar_aw:m1|always1~5" merged to single register "ram_dp_ar_aw:m1|always1~2"
Info: Duplicate register "ram_dp_ar_aw:m1|always1~6" merged to single register "ram_dp_ar_aw:m1|always1~2"
Info: Duplicate register "ram_dp_ar_aw:m1|always1~7" merged to single register "ram_dp_ar_aw:m1|always1~2"
Info: Duplicate register "ram_dp_ar_aw:m1|always1~8" merged to single register "ram_dp_ar_aw:m1|always1~2"
Info: Duplicate register "ram_dp_ar_aw:m1|always1~9" merged to single register "ram_dp_ar_aw:m1|always1~2"
Info: Duplicate register "ram_dp_ar_aw:m1|always1~10" merged to single register "ram_dp_ar_aw:m1|always1~2"
Info: Duplicate register "ram_dp_ar_aw:m1|always2~2" merged to single register "ram_dp_ar_aw:m1|always1~2"
Info: Duplicate register "ram_dp_ar_aw:m1|always2~3" merged to single register "ram_dp_ar_aw:m1|always1~2"
Info: Duplicate register "ram_dp_ar_aw:m1|always2~4" merged to single register "ram_dp_ar_aw:m1|always1~2"
Info: Duplicate register "ram_dp_ar_aw:m1|always2~5" merged to single register "ram_dp_ar_aw:m1|always1~2"
Info: Duplicate register "ram_dp_ar_aw:m1|always2~6" merged to single register "ram_dp_ar_aw:m1|always1~2"
Info: Duplicate register "ram_dp_ar_aw:m1|always2~7" merged to single register "ram_dp_ar_aw:m1|always1~2"
Info: Duplicate register "ram_dp_ar_aw:m1|always2~8" merged to single register "ram_dp_ar_aw:m1|always1~2"
Info: Duplicate register "ram_dp_ar_aw:m1|always2~9" merged to single register "ram_dp_ar_aw:m1|always1~2"
Info: State machine "|EPPTOP|EPP2SRAM:M0|epp_state" contains 5 states
Info: Selected Auto state machine encoding method for state machine "|EPPTOP|EPP2SRAM:M0|epp_state"
Info: Encoding result for state machine "|EPPTOP|EPP2SRAM:M0|epp_state"
Info: Completed encoding using 5 state bits
Info: Encoded state bit "EPP2SRAM:M0|epp_state.EPP_WAIT_ADDRREAD"
Info: Encoded state bit "EPP2SRAM:M0|epp_state.EPP_WAIT_ADDRWRITE"
Info: Encoded state bit "EPP2SRAM:M0|epp_state.EPP_WAIT_DATAREAD"
Info: Encoded state bit "EPP2SRAM:M0|epp_state.EPP_IDLE"
Info: Encoded state bit "EPP2SRAM:M0|epp_state.EPP_WAIT_DATAWRITE"
Info: State "|EPPTOP|EPP2SRAM:M0|epp_state.EPP_IDLE" uses code string "00000"
Info: State "|EPPTOP|EPP2SRAM:M0|epp_state.EPP_WAIT_DATAREAD" uses code string "00110"
Info: State "|EPPTOP|EPP2SRAM:M0|epp_state.EPP_WAIT_ADDRWRITE" uses code string "01010"
Info: State "|EPPTOP|EPP2SRAM:M0|epp_state.EPP_WAIT_ADDRREAD" uses code string "10010"
Info: State "|EPPTOP|EPP2SRAM:M0|epp_state.EPP_WAIT_DATAWRITE" uses code string "00011"
Warning: Converting TRI node "ram_dp_ar_aw:m1|data_0~26" that feeds logic to an OR gate
Warning: Converting TRI node "ram_dp_ar_aw:m1|data_0~30" that feeds logic to an OR gate
Warning: Converting TRI node "ram_dp_ar_aw:m1|data_0~34" that feeds logic to an OR gate
Warning: Converting TRI node "ram_dp_ar_aw:m1|data_0~38" that feeds logic to an OR gate
Warning: Converting TRI node "ram_dp_ar_aw:m1|data_0~42" that feeds logic to an OR gate
Warning: Converting TRI node "ram_dp_ar_aw:m1|data_0~46" that feeds logic to an OR gate
Warning: Converting TRI node "ram_dp_ar_aw:m1|data_0~50" that feeds logic to an OR gate
Warning: Converting TRI node "ram_dp_ar_aw:m1|data_0~54" that feeds logic to an OR gate
Warning: Output pins are stuck at VCC or GND
Warning: Pin "INT" stuck at GND
Info: 2 registers lost all their fanouts during netlist optimizations. The first 2 are displayed below.
Info: Register "M0/epp_state~119" lost all its fanouts during netlist optimizations.
Info: Register "M0/epp_state~120" lost all its fanouts during netlist optimizations.
Info: Implemented 212 device resources after synthesis - the final resource count might be different
Info: Implemented 11 input pins
Info: Implemented 2 output pins
Info: Implemented 16 bidirectional pins
Info: Implemented 183 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings
Info: Allocated 132 megabytes of memory during processing
Info: Processing ended: Tue Dec 30 21:43:07 2008
Info: Elapsed time: 00:00:04
+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in D:/montage/verilog code/EPPTOP V1.0/EPPTOP.map.smsg.
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