mpc5xx_hi.c

Coldfire MCF5282 DBug bootloader

	IRMD(USIU, RTCALK,	32)
	IRMD(USIU, PISCRK,	32)
	IRMD(USIU, PITCK,	32)
*/ /*will lock if you read these registers*/
	/*
	 * Clocks and Reset Keys
	 */
/*	IRMD(USIU, SCCRK,   32)
	IRMD(USIU, PLPRCRK, 32)
	IRMD(USIU, RSRK,    16)
*/ /*will lock if you read these registers*/
}

/****************************************************************************/
#ifdef CPU_MPC555
/*
 * Only the MPC555 has SRAM_A and SRAM_B
 */
static void
irmd_sram_a (char *reg, int regread, uint32 value)
{
	IRMD(SRAM_A, SRAMMCR, 32)
	IRMD(SRAM_A, SRAMTST, 32)
}

/****************************************************************************/
static void
irmd_sram_b (char *reg, int regread, uint32 value)
{
	IRMD(SRAM_B, SRAMMCR, 32)
	IRMD(SRAM_B, SRAMTST, 32)
}
#endif

/****************************************************************************/
#ifndef CPU_MPC555
/*
 * All parts except MPC555 have CALRAM_A
 */
static void
irmd_calram_a (char *reg, int regread, uint32 value)
{
	IRMD(CALRAM_A, CRAMMCR,		32)
	IRMD(CALRAM_A, CRAMTST,		32)
	IRMD(CALRAM_A, CRAM_RBA0,	32)
	IRMD(CALRAM_A, CRAM_RBA1,	32)
	IRMD(CALRAM_A, CRAM_RBA2,	32)
	IRMD(CALRAM_A, CRAM_RBA3,	32)
	IRMD(CALRAM_A, CRAM_RBA4,	32)
	IRMD(CALRAM_A, CRAM_RBA5,	32)
	IRMD(CALRAM_A, CRAM_RBA6,	32)
	IRMD(CALRAM_A, CRAM_RBA7,	32)
	IRMD(CALRAM_A, CRAMOTR,		32)
}
#endif

/****************************************************************************/
#if (defined(CPU_MPC565) || defined (CPU_MPC566))
/*
 * Only the MPC565/6 have CALRAM_B
 */
static void
irmd_calram_b (char *reg, int regread, uint32 value)
{
	IRMD(CALRAM_B, CRAMMCR,		32)
	IRMD(CALRAM_B, CRAMTST,		32)
	IRMD(CALRAM_B, CRAM_RBA0,	32)
	IRMD(CALRAM_B, CRAM_RBA1,	32)
	IRMD(CALRAM_B, CRAM_RBA2,	32)
	IRMD(CALRAM_B, CRAM_RBA3,	32)
	IRMD(CALRAM_B, CRAM_RBA4,	32)
	IRMD(CALRAM_B, CRAM_RBA5,	32)
	IRMD(CALRAM_B, CRAM_RBA6,	32)
	IRMD(CALRAM_B, CRAM_RBA7,	32)
	IRMD(CALRAM_B, CRAMOTR,		32)
}
#endif

/****************************************************************************/
/*
 * Common to all MPC5xx parts
 */
static void
irmd_uimb (char *reg, int regread, uint32 value)
{
	IRMD(UIMB, UMCR, 32)
	IRMD(UIMB, UTSTCREG, 32)
	IRMD(UIMB, UIPEND, 32)
}

/****************************************************************************/
/*
 * Common to all MPC5xx parts
 */
static void
irmd_tpu_a (char *reg, int regread, uint32 value)
{
	IRMD(TPU_A, TPUMCR,	16)
	IRMD(TPU_A, TICR,	16)
	IRMD(TPU_A, CIER,	16)
	IRMD(TPU_A, CFSR0,	16)
	IRMD(TPU_A, CFSR1,	16)
	IRMD(TPU_A, CFSR2,	16)
	IRMD(TPU_A, CFSR3,	16)
	IRMD(TPU_A, HSQR0,	16)
	IRMD(TPU_A, HSQR1,	16)
	IRMD(TPU_A, HSRR0,	16)
	IRMD(TPU_A, HSRR1,	16)
	IRMD(TPU_A, CPR0,	16)
	IRMD(TPU_A, CPR1,	16)
	IRMD(TPU_A, CISR,	16)
	IRMD(TPU_A, TPUMCR2,16)
	IRMD(TPU_A, TPUMCR3,16)
}

/****************************************************************************/
/*
 * Common to all MPC5xx parts
 */
static void
irmd_tpu_b (char *reg, int regread, uint32 value)
{
	IRMD(TPU_B, TPUMCR,	16)
	IRMD(TPU_B, TICR,	16)
	IRMD(TPU_B, CIER,	16)
	IRMD(TPU_B, CFSR0,	16)
	IRMD(TPU_B, CFSR1,	16)
	IRMD(TPU_B, CFSR2,	16)
	IRMD(TPU_B, CFSR3,	16)
	IRMD(TPU_B, HSQR0,	16)
	IRMD(TPU_B, HSQR1,	16)
	IRMD(TPU_B, HSRR0,	16)
	IRMD(TPU_B, HSRR1,	16)
	IRMD(TPU_B, CPR0,	16)
	IRMD(TPU_B, CPR1,	16)
	IRMD(TPU_B, CISR,	16)
	IRMD(TPU_B, TPUMCR2,16)
	IRMD(TPU_B, TPUMCR3,16)
}

/****************************************************************************/
#if (defined (CPU_MPC565) || defined (CPU_MPC566))
/*
 * Only the MPC565/6 have TPU3_C
 */
static void
irmd_tpu_c (char *reg, int regread, uint32 value)
{
	IRMD(TPU_C, TPUMCR,	16)
	IRMD(TPU_C, TICR,	16)
	IRMD(TPU_C, CIER,	16)
	IRMD(TPU_C, CFSR0,	16)
	IRMD(TPU_C, CFSR1,	16)
	IRMD(TPU_C, CFSR2,	16)
	IRMD(TPU_C, CFSR3,	16)
	IRMD(TPU_C, HSQR0,	16)
	IRMD(TPU_C, HSQR1,	16)
	IRMD(TPU_C, HSRR0,	16)
	IRMD(TPU_C, HSRR1,	16)
	IRMD(TPU_C, CPR0,	16)
	IRMD(TPU_C, CPR1,	16)
	IRMD(TPU_C, CISR,	16)
	IRMD(TPU_C, TPUMCR2,16)
	IRMD(TPU_C, TPUMCR3,16)
}
#endif

/****************************************************************************/
static void
/*
 * Common to all MPC5xx parts
 */
irmd_can_a (char *reg, int regread, uint32 value)
{
	IRMD(CAN_A, TCNMCR,		16)
	IRMD(CAN_A, CANICR,		16)
	IRMD(CAN_A, CANCTRL0,	8)
	IRMD(CAN_A, CANCTRL1,	8)
	IRMD(CAN_A, PRESDIV,	8)
	IRMD(CAN_A, CANCTRL2,	8)
	IRMD(CAN_A, TIMER,		16)
	IRMD(CAN_A, RXGMSKHI,	16)
	IRMD(CAN_A, RXGMSKLO,	16)
	IRMD(CAN_A, RX14MSKHI,	16)
	IRMD(CAN_A, RX14MSKLO,	16)
	IRMD(CAN_A, RX15MSKHI,	16)
	IRMD(CAN_A, RX15MSKLO,	16)
	IRMD(CAN_A, ESTAT,		16)
	IRMD(CAN_A, IMASK,		16)
	IRMD(CAN_A, IFLAG,		16)
	IRMD(CAN_A, RXECTR,		8)
	IRMD(CAN_A, TXECTR,		8)
}

/****************************************************************************/
/*
 * Common to all MPC5xx parts
 */
static void
irmd_can_b (char *reg, int regread, uint32 value)
{
	IRMD(CAN_B, TCNMCR,		16)
	IRMD(CAN_B, CANICR,		16)
	IRMD(CAN_B, CANCTRL0,	8)
	IRMD(CAN_B, CANCTRL1,	8)
	IRMD(CAN_B, PRESDIV,	8)
	IRMD(CAN_B, CANCTRL2,	8)
	IRMD(CAN_B, TIMER,		16)
	IRMD(CAN_B, RXGMSKHI,	16)
	IRMD(CAN_B, RXGMSKLO,	16)
	IRMD(CAN_B, RX14MSKHI,	16)
	IRMD(CAN_B, RX14MSKLO,	16)
	IRMD(CAN_B, RX15MSKHI,	16)
	IRMD(CAN_B, RX15MSKLO,	16)
	IRMD(CAN_B, ESTAT,		16)
	IRMD(CAN_B, IMASK,		16)
	IRMD(CAN_B, IFLAG,		16)
	IRMD(CAN_B, RXECTR,		8)
	IRMD(CAN_B, TXECTR,		8)
}

/****************************************************************************/
#ifndef CPU_MPC555
/*
 * All parts except MPC555 have CALRAM_A
 */
static void
irmd_can_c (char *reg, int regread, uint32 value)
{
	IRMD(CAN_C, TCNMCR,		16)
	IRMD(CAN_C, CANICR,		16)
	IRMD(CAN_C, CANCTRL0,	8)
	IRMD(CAN_C, CANCTRL1,	8)
	IRMD(CAN_C, PRESDIV,	8)
	IRMD(CAN_C, CANCTRL2,	8)
	IRMD(CAN_C, TIMER,		16)
	IRMD(CAN_C, RXGMSKHI,	16)
	IRMD(CAN_C, RXGMSKLO,	16)
	IRMD(CAN_C, RX14MSKHI,	16)
	IRMD(CAN_C, RX14MSKLO,	16)
	IRMD(CAN_C, RX15MSKHI,	16)
	IRMD(CAN_C, RX15MSKLO,	16)
	IRMD(CAN_C, ESTAT,		16)
	IRMD(CAN_C, IMASK,		16)
	IRMD(CAN_C, IFLAG,		16)
	IRMD(CAN_C, RXECTR,		8)
	IRMD(CAN_C, TXECTR,		8)
}
#endif

/****************************************************************************/
#if (defined (CPU_MPC565) || defined (CPU_MPC566))
/*
 * Only the MPC565/6 have a Data Link Controller Module
 */
static void
irmd_dlcmd2 (char *reg, int regread, uint32 value)
{
	IRMD(DLCMD2, DLCMCR,	16)
	IRMD(DLCMD2, DLCTCR,	16)
	IRMD(DLCMD2, DLCIPR,	16)
	IRMD(DLCMD2, DLCILR,	8)
	IRMD(DLCMD2, DLCIVR,	8)
	IRMD(DLCMD2, DLCSCTL,	16)
	IRMD(DLCMD2, DLCSDATA,	16)
	IRMD(DLCMD2, DLCCMD,	8)
	IRMD(DLCMD2, DLCTDATA,	8)
	IRMD(DLCMD2, DLCSTAT,	8)
	IRMD(DLCMD2, DLCRDATA,	8)
}
#endif

/****************************************************************************/
#ifdef CPU_MPC555
/*
 * The MPC555 has the "original" QSMCM
 */
static void
irmd_qsmcm (char *reg, int regread, uint32 value)
{
	IRMD(QSMCM, QSMCR,		16)
	IRMD(QSMCM, QDSCI_IL,	16)
	IRMD(QSMCM, QSPI_IL,	16)
	IRMD(QSMCM, SCC1R0,		16)
	IRMD(QSMCM, SCC1R1,		16)
	IRMD(QSMCM, SC1SR,		16)
	IRMD(QSMCM, SC1DR,		16)
	IRMD(QSMCM, PORTQS,		16)
	IRMD(QSMCM, PQSPAR,		8)
	IRMD(QSMCM, DDRQS,		8)
	IRMD(QSMCM, SPCR0,		16)
	IRMD(QSMCM, SPCR1,		16)
	IRMD(QSMCM, SPCR2,		16)
	IRMD(QSMCM, SPCR3,		8)
	IRMD(QSMCM, SPSR,		8)
	IRMD(QSMCM, SCC2R0,		16)
	IRMD(QSMCM, SCC2R1,		16)
	IRMD(QSMCM, SC2SR,		16)
	IRMD(QSMCM, SC2DR,		16)
	IRMD(QSMCM, QSCI1CR,	16)
	IRMD(QSMCM, QSCI1SR,	16)
/*	IRMD(QSMCM, SCTQ[16],	16)
	IRMD(QSMCM, SCRQ[16],	16)
	IRMD(QSMCM, RECRAM[32],	16)
	IRMD(QSMCM, TRANRAM[32],16)
	IRMD(QSMCM, COMDRAM[32],16)
*/
}
#endif

/****************************************************************************/
#ifndef CPU_MPC555
/*
 * All others have the enhanced QSMCM
 */
static void
irmd_qsmcm_a (char *reg, int regread, uint32 value)
{
	IRMD(QSMCM_A, QSMCR,	16)
	IRMD(QSMCM_A, QDSCI_IL,	16)
	IRMD(QSMCM_A, QSPI_IL,	16)
	IRMD(QSMCM_A, SCC1R0,	16)
	IRMD(QSMCM_A, SCC1R1,	16)
	IRMD(QSMCM_A, SC1SR,	16)
	IRMD(QSMCM_A, SC1DR,	16)
	IRMD(QSMCM_A, PORTQS,	16)
	IRMD(QSMCM_A, PQSPAR,	8)
	IRMD(QSMCM_A, DDRQS,	8)
	IRMD(QSMCM_A, SPCR0,	16)
	IRMD(QSMCM_A, SPCR1,	16)
	IRMD(QSMCM_A, SPCR2,	16)
	IRMD(QSMCM_A, SPCR3,	8)
	IRMD(QSMCM_A, SPSR,		8)
	IRMD(QSMCM_A, SCC2R0,	16)
	IRMD(QSMCM_A, SCC2R1,	16)
	IRMD(QSMCM_A, SC2SR,	16)
	IRMD(QSMCM_A, SC2DR,	16)
	IRMD(QSMCM_A, QSCI1CR,	16)
	IRMD(QSMCM_A, QSCI1SR,	16)

/*	IRMD(QSMCM_A, SCTQ[0],	16)
	IRMD(QSMCM_A, SCTQ[1],	16)
	IRMD(QSMCM_A, SCTQ[2],	16)
	IRMD(QSMCM_A, SCTQ[3],	16)
*/
}
#endif

/****************************************************************************/
#if (defined (CPU_MPC565) || defined (CPU_MPC566))
/*
 * The MPC565/6 have a second QSMCM module
 */
static void
irmd_qsmcm_b (char *reg, int regread, uint32 value)
{
	IRMD(QSMCM_B, QSMCR,	16)
	IRMD(QSMCM_B, QDSCI_IL,	16)
	IRMD(QSMCM_B, QSPI_IL,	16)
	IRMD(QSMCM_B, SCC1R0,	16)
	IRMD(QSMCM_B, SCC1R1,	16)
	IRMD(QSMCM_B, SC1SR,	16)
	IRMD(QSMCM_B, SC1DR,	16)
	IRMD(QSMCM_B, PORTQS,	16)
	IRMD(QSMCM_B, PQSPAR,	8)
	IRMD(QSMCM_B, DDRQS,	8)
	IRMD(QSMCM_B, SPCR0,	16)
	IRMD(QSMCM_B, SPCR1,	16)
	IRMD(QSMCM_B, SPCR2,	16)
	IRMD(QSMCM_B, SPCR3,	8)
	IRMD(QSMCM_B, SPSR,		8)
	IRMD(QSMCM_B, SCC2R0,	16)
	IRMD(QSMCM_B, SCC2R1,	16)
	IRMD(QSMCM_B, SC2SR,	16)
	IRMD(QSMCM_B, SC2DR,	16)
	IRMD(QSMCM_B, QSCI1CR,	16)
	IRMD(QSMCM_B, QSCI1SR,	16)
/*	IRMD(QSMCM_B, SCTQ[0],	16)
	IRMD(QSMCM_B, SCTQ[1],	16)
	IRMD(QSMCM_B, SCTQ[2],	16)
	IRMD(QSMCM_B, SCTQ[3],	16)
*/
}
#endif

/*********************************************************************/
/* 
 * All parts have QADC_A
 */
static void
irmd_qadc_a (char *reg, int regread, uint32 value)
{
	IRMD(QADC_A, QADC64MCR,	16)
	IRMD(QADC_A, QADC64INT,	16)
	IRMD(QADC_A, PORTQA,	8)
	IRMD(QADC_A, PORTQB,	8)
	IRMD(QADC_A, DDRQA,		16)
	IRMD(QADC_A, QACR0,		16)
	IRMD(QADC_A, QACR1,		16)
	IRMD(QADC_A, QACR2,		16)
	IRMD(QADC_A, QASR0,		16)
	IRMD(QADC_A, QASR1,		16)
/*	IRMD(QADC_A, CCW[64],	16)
	IRMD(QADC_A, RJURR[64],	16)
	IRMD(QADC_A, LJSRR[64],	16)
	IRMD(QADC_A, LJURR[64],	16)
*/
}

/*********************************************************************/
/* 
 * All parts have QADC_B
 */
static void
irmd_qadc_b (char *reg, int regread, uint32 value)
{
	IRMD(QADC_B, QADC64MCR,	16)
	IRMD(QADC_B, QADC64INT,	16)
	IRMD(QADC_B, PORTQA,	8)
	IRMD(QADC_B, PORTQB,	8)
	IRMD(QADC_B, DDRQA,		16)
	IRMD(QADC_B, QACR0,		16)
	IRMD(QADC_B, QACR1,		16)
	IRMD(QADC_B, QACR2,		16)
	IRMD(QADC_B, QASR0,		16)
	IRMD(QADC_B, QASR1,		16)
/*	IRMD(QADC_B, CCW[64],	16)
	IRMD(QADC_B, RJURR[64],	16)
	IRMD(QADC_B, LJSRR[64],	16)
	IRMD(QADC_B, LJURR[64],	16)
*/
}
/*********************************************************************/
#ifdef CPU_MPC555
/*
 * The MPC555 has the MIOS1
 */
static void
irmd_mios1 (char *reg, int regread, uint32 value)
{
	IRMD(MIOS1, MPWMSM0PERR,	16)
	IRMD(MIOS1, MPWMSM0PULR,	16)
	IRMD(MIOS1, MPWMSM0CNTR,	16)
	IRMD(MIOS1, MPWMSM0SCR,		16)
	IRMD(MIOS1, MPWMSM1PERR,	16)
	IRMD(MIOS1, MPWMSM1PULR,	16)
	IRMD(MIOS1, MPWMSM1CNTR,	16)
	IRMD(MIOS1, MPWMSM1SCR,		16)
	IRMD(MIOS1, MPWMSM2PERR,	16)
	IRMD(MIOS1, MPWMSM2PULR,	16)
	IRMD(MIOS1, MPWMSM2CNTR,	16)
	IRMD(MIOS1, MPWMSM2SCR,		16)
	IRMD(MIOS1, MPWMSM3PERR,	16)
	IRMD(MIOS1, MPWMSM3PULR,	16)
	IRMD(MIOS1, MPWMSM3CNTR,	16)
	IRMD(MIOS1, MPWMSM3SCR,		16)
	IRMD(MIOS1, MMCSM6CNT,		16)
	IRMD(MIOS1, MMCSM6MLR,		16)
	IRMD(MIOS1, MMCSM6SCR,		16)
	IRMD(MIOS1, MDASM11AR,		16)
	IRMD(MIOS1, MDASM11BR,		16)
	IRMD(MIOS1, MDASM11SCR,		16)
	IRMD(MIOS1, MDASM12AR,		16)
	IRMD(MIOS1, MDASM12BR,		16)
	IRMD(MIOS1, MDASM12SCR,		16)
	IRMD(MIOS1, MDASM13AR,		16)
	IRMD(MIOS1, MDASM13BR,		16)
	IRMD(MIOS1, MDASM13SCR,		16)
	IRMD(MIOS1, MDASM14AR,		16)
	IRMD(MIOS1, MDASM14BR,		16)
	IRMD(MIOS1, MDASM14SCR,		16)
	IRMD(MIOS1, MDASM15AR,		16)
	IRMD(MIOS1, MDASM15BR,		16)
	IRMD(MIOS1, MDASM15SCR,		16)
	IRMD(MIOS1, MPWMSM16PERR,	16)
	IRMD(MIOS1, MPWMSM16PULR,	16)
	IRMD(MIOS1, MPWMSM16CNTR,	16)
	IRMD(MIOS1, MPWMSM16SCR,	16)
	IRMD(MIOS1, MPWMSM17PERR,	16)
	IRMD(MIOS1, MPWMSM17PULR,	16)
	IRMD(MIOS1, MPWMSM17CNTR,	16)
	IRMD(MIOS1, MPWMSM17SCR,	16)
	IRMD(MIOS1, MPWMSM18PERR,	16)
	IRMD(MIOS1, MPWMSM18PULR,	16)
	IRMD(MIOS1, MPWMSM18CNTR,	16)
	IRMD(MIOS1, MPWMSM18SCR,	16)
	IRMD(MIOS1, MPWMSM19PERR,	16)
	IRMD(MIOS1, MPWMSM19PULR,	16)
	IRMD(MIOS1, MPWMSM19CNTR,	16)
	IRMD(MIOS1, MPWMSM19SCR,	16)
	IRMD(MIOS1, MMCSM22CNT,		16)
	IRMD(MIOS1, MMCSM22MLR,		16)
	IRMD(MIOS1, MMCSM22SCR,		16)
	IRMD(MIOS1, MDASM27AR,		16)
	IRMD(MIOS1, MDASM27BR,		16)
	IRMD(MIOS1, MDASM27SCR,		16)
	IRMD(MIOS1, MDASM28AR,		16)
	IRMD(MIOS1, MDASM28BR,		16)
	IRMD(MIOS1, MDASM28SCR,		16)
	IRMD(MIOS1, MDASM29AR,		16)
	IRMD(MIOS1, MDASM29BR,		16)
	IRMD(MIOS1, MDASM29SCR,		16)
	IRMD(MIOS1, MDASM30AR,		16)
	IRMD(MIOS1, MDASM30BR,		16)
	IRMD(MIOS1, MDASM30SCR,		16)
	IRMD(MIOS1, MDASM31AR,		16)
	IRMD(MIOS1, MDASM31BR,		16)
	IRMD(MIOS1, MDASM31SCR,		16)
	IRMD(MIOS1, MPIOSM32DR,		16)
	IRMD(MIOS1, MPIOSM32DDR,	16)
	IRMD(MIOS1, MIOS1TPCR,		16)
	IRMD(MIOS1, MIOS1VNR,		16)
	IRMD(MIOS1, MIOS1MCR,		16)
	IRMD(MIOS1, MCPSMSCR,		16)
	IRMD(MIOS1, MIOS1SR0,		16)
	IRMD(MIOS1, MIOS1ER0,		16)
	IRMD(MIOS1, MIOS1RPR0,		16)
	IRMD(MIOS1, MIOS1LVL0,		16)
	IRMD(MIOS1, MIOS1SR1,		16)
	IRMD(MIOS1, MIOS1ER1,		16)
	IRMD(MIOS1, MIOS1RPR1,		16)
	IRMD(MIOS1, MIOS1LVL1,		16)
}
/*********************************************************************/
#else
/*
 * All others have the MIOS14
 */
static void
irmd_mios14 (char *reg, int regread, uint32 value)
{
	IRMD(MIOS14, MPWMSM0PERR,	16)
	IRMD(MIOS14, MPWMSM0PULR,	16)
	IRMD(MIOS14, MPWMSM0CNTR,	16)
	IRMD(MIOS14, MPWMSM0SCR,	16)
	IRMD(MIOS14, MPWMSM1PERR,	16)
	IRMD(MIOS14, MPWMSM1PULR,	16)
	IRMD(MIOS14, MPWMSM1CNTR,	16)
	IRMD(MIOS14, MPWMSM1SCR,	16)
	IRMD(MIOS14, MPWMSM2PERR,	16)
	IRMD(MIOS14, MPWMSM2PULR,	16)
	IRMD(MIOS14, MPWMSM2CNTR,	16)
	IRMD(MIOS14, MPWMSM2SCR,	16)
	IRMD(MIOS14, MPWMSM3PERR,	16)
	IRMD(MIOS14, MPWMSM3PULR,	16)
	IRMD(MIOS14, MPWMSM3CNTR,	16)
	IRMD(MIOS14, MPWMSM3SCR,	16)
	IRMD(MIOS14, MPWMSM4PERR,	16)
	IRMD(MIOS14, MPWMSM4PULR,	16)
	IRMD(MIOS14, MPWMSM4CNTR,	16)
	IRMD(MIOS14, MPWMSM4SCR,	16)
	IRMD(MIOS14, MPWMSM5PERR,	16)
	IRMD(MIOS14, MPWMSM5PULR,	16)
	IRMD(MIOS14, MPWMSM5CNTR,	16)
	IRMD(MIOS14, MPWMSM5SCR,	16)
	IRMD(MIOS14, MMCSM6CNT,		16)
	IRMD(MIOS14, MMCSM6MLR,		16)
	IRMD(MIOS14, MMCSM6SCR,		16)
	IRMD(MIOS14, MMCSM7CNT,		16)
	IRMD(MIOS14, MMCSM7MLR,		16)
	IRMD(MIOS14, MMCSM7SCR,		16)
	IRMD(MIOS14, MMCSM8CNT,		16)
	IRMD(MIOS14, MMCSM8MLR,		16)
	IRMD(MIOS14, MMCSM8SCR,		16)
#ifdef _MIOS14_RTC
	if ((strcasecmp("MRTCSMFRCH",reg) == 0) || display_all)	\
	{														\
		if (regread)										\
		{													\
			printf(FORMAT16, "MRTCSMFRCH",					\
				MIOS14.MRTCSMFRC.R.H );						\
			pause(&displayed);								\
		}													\