mpc6xx_lo.s

Coldfire MCF5282 DBug bootloader

	eieio
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######################################################################

#
# These routines read and write the special purpose registers of the
# MPC6XX.  In general, all writes accept a single 32-bit operand in r3,
# and all reads return a 32-bit operand in r3.  Proper synchronization
# is inserted where appropriate.
#
# C prototypes look like:
#
# void   mpc6xx_wr_XXX (uint32 data);
# uint32 mpc6xx_rd_XXX (void);
#


	#
	# MSR
	#
mpc6xx_wr_msr:
	sync
	mtmsr	r3
	isync
	sync
	blr

mpc6xx_rd_msr:
	mfmsr	r3
	isync
	blr

	#
	# SR0-15
	#
mpc6xx_wr_sr0:
mpc6xx_wr_sr1:
mpc6xx_wr_sr2:
mpc6xx_wr_sr3:
mpc6xx_wr_sr4:
mpc6xx_wr_sr5:
mpc6xx_wr_sr6:
mpc6xx_wr_sr7:
mpc6xx_wr_sr8:
mpc6xx_wr_sr9:
mpc6xx_wr_sr10:
mpc6xx_wr_sr11:
mpc6xx_wr_sr12:
mpc6xx_wr_sr13:
mpc6xx_wr_sr14:
mpc6xx_wr_sr15:
	sync
	mtsr	sr0,r3
	sync
	blr

mpc6xx_rd_sr0:
mpc6xx_rd_sr1:
mpc6xx_rd_sr2:
mpc6xx_rd_sr3:
mpc6xx_rd_sr4:
mpc6xx_rd_sr5:
mpc6xx_rd_sr6:
mpc6xx_rd_sr7:
mpc6xx_rd_sr8:
mpc6xx_rd_sr9:
mpc6xx_rd_sr10:
mpc6xx_rd_sr11:
mpc6xx_rd_sr12:
mpc6xx_rd_sr13:
mpc6xx_rd_sr14:
mpc6xx_rd_sr15:
	sync
	mfsr	r3,sr0
	blr

	#
	# TBL
	#
mpc6xx_wr_tbl:
	mtspr	284,r3
	blr

mpc6xx_wr_tbu:
	mtspr	285,r3
	blr

	#
	# TBU
	#
mpc6xx_rd_tbl:
	mftb	r3,268
	blr

mpc6xx_rd_tbu:
	mftb	r3,269
	blr

	#
	# PVR
	#
mpc6xx_rd_pvr:
	mfspr	r3,spr_pvr
	blr

	#
	# IBAT0
	#
mpc6xx_wr_ibat0u:
	sync
	mtspr	spr_ibat0u,r3
	isync
	blr

mpc6xx_rd_ibat0u:
	mfspr	r3,spr_ibat0u
	blr

mpc6xx_wr_ibat0l:
	sync
	mtspr	spr_ibat0l,r3
	isync
	blr

mpc6xx_rd_ibat0l:
	mfspr	r3,spr_ibat0l
	blr

	#
	# IBAT1
	#
mpc6xx_wr_ibat1u:
	sync
	mtspr	spr_ibat1u,r3
	isync
	blr

mpc6xx_rd_ibat1u:
	mfspr	r3,spr_ibat1u
	blr

mpc6xx_wr_ibat1l:
	sync
	mtspr	spr_ibat1l,r3
	isync
	blr

mpc6xx_rd_ibat1l:
	mfspr	r3,spr_ibat1l
	blr

	#
	# IBAT2
	#
mpc6xx_wr_ibat2u:
	sync
	mtspr	spr_ibat2u,r3
	isync
	blr

mpc6xx_rd_ibat2u:
	mfspr	r3,spr_ibat2u
	blr

mpc6xx_wr_ibat2l:
	sync
	mtspr	spr_ibat2l,r3
	isync
	blr

mpc6xx_rd_ibat2l:
	mfspr	r3,spr_ibat2l
	blr

	#
	# IBAT3
	#
mpc6xx_wr_ibat3u:
	sync
	mtspr	spr_ibat3u,r3
	isync
	blr

mpc6xx_rd_ibat3u:
	mfspr	r3,spr_ibat3u
	blr

mpc6xx_wr_ibat3l:
	sync
	mtspr	spr_ibat3l,r3
	isync
	blr

mpc6xx_rd_ibat3l:
	mfspr	r3,spr_ibat3l
	blr

	#
	# DBAT0
	#
mpc6xx_wr_dbat0u:
	sync
	mtspr	spr_dbat0u,r3
	isync
	blr

mpc6xx_rd_dbat0u:
	mfspr	r3,spr_dbat0u
	blr

mpc6xx_wr_dbat0l:
	sync
	mtspr	spr_dbat0l,r3
	isync
	blr

mpc6xx_rd_dbat0l:
	mfspr	r3,spr_dbat0l
	blr

	#
	# DBAT1
	#
mpc6xx_wr_dbat1u:
	sync
	mtspr	spr_dbat1u,r3
	isync
	blr

mpc6xx_rd_dbat1u:
	mfspr	r3,spr_dbat1u
	blr

mpc6xx_wr_dbat1l:
	sync
	mtspr	spr_dbat1l,r3
	isync
	blr

mpc6xx_rd_dbat1l:
	mfspr	r3,spr_dbat1l
	blr

	#
	# DBAT2
	#
mpc6xx_wr_dbat2u:
	sync
	mtspr	spr_dbat2u,r3
	isync
	blr

mpc6xx_rd_dbat2u:
	mfspr	r3,spr_dbat2u
	blr

mpc6xx_wr_dbat2l:
	sync
	mtspr	spr_dbat2l,r3
	isync
	blr

mpc6xx_rd_dbat2l:
	mfspr	r3,spr_dbat2l
	blr

	#
	# DBAT3
	#
mpc6xx_wr_dbat3u:
	sync
	mtspr	spr_dbat3u,r3
	isync
	blr

mpc6xx_rd_dbat3u:
	mfspr	r3,spr_dbat3u
	blr

mpc6xx_wr_dbat3l:
	sync
	mtspr	spr_dbat3l,r3
	isync
	blr

mpc6xx_rd_dbat3l:
	mfspr	r3,spr_dbat3l
	blr

	#
	# SDR1
	#
mpc6xx_wr_sdr1:
	sync
	mtspr	spr_sdr1,r3
	isync
	blr

mpc6xx_rd_sdr1:
	mfspr	r3,spr_sdr1
	blr

	#
	# DAR
	#
mpc6xx_wr_dar:
	sync
	mtspr	spr_dar,r3
	isync
	blr

mpc6xx_rd_dar:
	mfspr	r3,spr_dar
	blr

	#
	# DSISR
	#
mpc6xx_wr_dsisr:
	sync
	mtspr	spr_dsisr,r3
	isync
	blr

mpc6xx_rd_dsisr:
	mfspr	r3,spr_dsisr
	blr

	#
	# DEC
	#
mpc6xx_wr_dec:
	sync
	mtspr	spr_dec,r3
	isync
	blr

mpc6xx_rd_dec:
	mfspr	r3,spr_dec
	blr


	#
	# MPC60x HID0
	#
mpc603_wr_hid0:
mpc603e_wr_hid0:
mpc604_wr_hid0:
mpc604e_wr_hid0:
mpc750_wr_hid0:
	sync
	mtspr	spr_603_hid0,r3
	isync
	sync
	blr

mpc603_rd_hid0:
mpc603e_rd_hid0:
mpc604_rd_hid0:
mpc604e_rd_hid0:
mpc750_rd_hid0:
	mfspr	r3,spr_603_hid0
	blr

	#
	# MPC603 DMISS
	#
mpc603_wr_dmiss:
mpc603e_wr_dmiss:
	mtspr	spr_603_dmiss,r3
	isync
	sync
	blr

mpc603_rd_dmiss:
mpc603e_rd_dmiss:
	mfspr	r3,spr_603_dmiss
	blr

	#
	# MPC603 DCMP
	#
mpc603_wr_dcmp:
mpc603e_wr_dcmp:
	mtspr	spr_603_dcmp,r3
	isync
	sync
	blr

mpc603_rd_dcmp:
mpc603e_rd_dcmp:
	mfspr	r3,spr_603_dcmp
	blr

	#
	# MPC603 HASH1
	#
mpc603_rd_hash1:
mpc603e_rd_hash1:
	mfspr	r3,spr_603_hash1
	blr

	#
	# MPC603 HASH2
	#
mpc603_rd_hash2:
mpc603e_rd_hash2:
	mfspr	r3,spr_603_hash2
	blr

	#
	# MPC603 IMISS
	#
mpc603_wr_imiss:
mpc603e_wr_imiss:
	mfspr	r3,spr_603_imiss
	blr

mpc603_rd_imiss:
mpc603e_rd_imiss:
	mfspr	r3,spr_603_imiss
	blr

	#
	# MPC603 ICMP
	#
mpc603_wr_icmp:
mpc603e_wr_icmp:
	mtspr	spr_603_icmp,r3
	isync
	sync
	blr

mpc603e_rd_icmp:
	mfspr	r3,spr_603_icmp
	blr

	#
	# MPC603 RPA
	#
mpc603_wr_rpa:
mpc603e_wr_rpa:
	mtspr	spr_603_rpa,r3
	isync
	sync
	blr

mpc603_rd_rpa:
mpc603e_rd_rpa:
	mfspr	r3,spr_603_rpa
	blr

	#
	# MPC60X IABR
	#
mpc603_wr_iabr:
mpc603e_wr_iabr:
mpc604_wr_iabr:
mpc604e_wr_iabr:
mpc750_wr_iabr:
	mtspr	spr_603_iabr,r3
	isync
	sync
	blr

mpc603_rd_iabr:
mpc603e_rd_iabr:
mpc604_rd_iabr:
mpc604e_rd_iabr:
mpc750_rd_iabr:
	mfspr	r3,spr_603_iabr
	blr

	#
	# MPC60X EAR
	#
mpc603_rd_ear:
mpc603e_rd_ear:
mpc604_rd_ear:
mpc604e_rd_ear:
mpc750_rd_ear:
	sync
	mfspr	r3,spr_603_ear
	blr

mpc603_wr_ear:
mpc603e_wr_ear:
mpc604_wr_ear:
mpc604e_wr_ear:
mpc750_wr_ear:
	sync
	mtspr	spr_603_ear,r3
	blr

	#
	# MPC603e,604e HID1
	#
mpc603e_rd_hid1:
mpc604e_rd_hid1:
mpc750_rd_hid1:
	mfspr	r3,spr_603e_hid1
	blr


	#
	# MPC604/604e/750 PMC1 PMC2 MMCR0
	#
mpc604_rd_pmc1:
mpc604e_rd_pmc1:
mpc750_rd_pmc1:
	sync
	mfspr	r3,spr_604_pmc1
	blr

mpc604_rd_pmc2:
mpc604e_rd_pmc2:
mpc750_rd_pmc2:
	sync
	mfspr	r3,spr_604_pmc2
	blr

mpc604_wr_mmcr0:
mpc604e_wr_mmcr0:
mpc750_wr_mmcr0:
	sync
	mtspr	spr_604_mmcr0,r3
	blr

mpc604_rd_mmcr0:
mpc604e_rd_mmcr0:
mpc750_rd_mmcr0:
	sync
	mfspr	r3,spr_604_mmcr0
	blr

	#
	# MPC604/604e SDA
	#
mpc604_rd_sda:
mpc604e_rd_sda:
	sync
	mfspr	r3,spr_604_sda
	blr

	#
	# MPC604/604e/750 SIA
	#
mpc604_rd_sia:
	sync
	mfspr	r3,spr_604_sia
	blr

	#
	# MPC604,604e,750 DABR
	#
mpc604_wr_dabr:
mpc604e_wr_dabr:
mpc750_wr_dabr:
	mtspr	spr_604_dabr,r3
	isync
	sync
	blr

mpc604_rd_dabr:
mpc604e_rd_dabr:
mpc750_rd_dabr:
	mfspr	r3,spr_604_dabr
	blr

	#
	# MPC604/604e PIR
	#
mpc604_rd_pir:
	sync
	mfspr	r3,spr_604_pir
	blr

	#
	# MPC750 UPMC1,2,3,4, USIA, UMMCR0,1
	#
mpc750_rd_upmc1:
	sync
	mfspr	r3,spr_750_upmc1
	blr

mpc750_rd_upmc2:
	sync
	mfspr	r3,spr_750_upmc2
	blr

mpc750_rd_upmc3:
	sync
	mfspr	r3,spr_750_upmc3
	blr

mpc750_rd_upmc4:
	sync
	mfspr	r3,spr_750_upmc4
	blr

mpc750_rd_usia:
	sync
	mfspr	r3,spr_750_usia
	blr

mpc750_rd_ummcr0:
	sync
	mfspr	r3,spr_750_ummcr0
	blr

mpc750_rd_ummcr1:
	sync
	mfspr	r3,spr_750_ummcr1
	blr

	#
	# MPC750 PMC3 PMC4 MMCR1
	#
mpc750_rd_pmc3:
	sync
	mfspr	r3,spr_750_pmc3
	blr

mpc750_rd_pmc4:
	sync
	mfspr	r3,spr_750_pmc4
	blr

mpc750_wr_mmcr1:
	sync
	mtspr	spr_750_mmcr1,r3
	blr

mpc750_rd_mmcr1:
	sync
	mfspr	r3,spr_750_mmcr1
	blr

	#
	# MPC750 THRM1,2,3
	#
mpc750_wr_thrm1:
	sync
	mtspr	spr_750_thrm1,r3
	blr

mpc750_rd_thrm1:
	sync
	mfspr	r3,spr_750_thrm1
	blr

mpc750_wr_thrm2:
	sync
	mtspr	spr_750_thrm2,r3
	blr

mpc750_rd_thrm2:
	sync
	mfspr	r3,spr_750_thrm2
	blr

mpc750_wr_thrm3:
	sync
	mtspr	spr_750_thrm3,r3
	blr

mpc750_rd_thrm3:
	sync
	mfspr	r3,spr_750_thrm3
	blr

	#
	# MPC750 ICTC
	#
mpc750_wr_ictc:
	sync
	mtspr	spr_750_ictc,r3
	isync
	blr

mpc750_rd_ictc:
	sync
	mfspr	r3,spr_750_ictc
	blr

	#
	# MPC750 L2CR
	#
mpc750_wr_l2cr:
	sync
	mtspr	spr_750_l2cr,r3
	isync
	blr

mpc750_rd_l2cr:
	sync
	mfspr	r3,spr_750_l2cr
	blr

######################################################################

	.end