mpc6xx_lo.s

Coldfire MCF5282 DBug bootloader

	mtspr	spr_ibat1u,r30	# spr530
	mtspr	spr_ibat1l,r30	# spr531
	mtspr	spr_ibat2u,r30	# spr532
	mtspr	spr_ibat2l,r30	# spr533
	mtspr	spr_ibat3u,r30	# spr534
	mtspr	spr_ibat3l,r30	# spr535

	mtspr	spr_dbat0u,r30	# spr536
	mtspr	spr_dbat0l,r30	# spr537
	mtspr	spr_dbat1u,r30	# spr538
	mtspr	spr_dbat1l,r30	# spr539
	mtspr	spr_dbat2u,r30	# spr540
	mtspr	spr_dbat2l,r30	# spr541
	mtspr	spr_dbat3u,r30	# spr542
	mtspr	spr_dbat3l,r30	# spr543
	isync

	mtsr	sr0,r30			# Clear out Segment Registers
	mtsr	sr1,r30
	mtsr	sr2,r30
	mtsr	sr3,r30
	mtsr	sr4,r30
	mtsr	sr5,r30
	mtsr	sr6,r30
	mtsr	sr7,r30
	mtsr	sr8,r30
	mtsr	sr9,r30
	mtsr	sr10,r30
	mtsr	sr11,r30
	mtsr	sr12,r30
	mtsr	sr13,r30
	mtsr	sr14,r30
	mtsr	sr15,r30
	isync

	mtspr	spr_sdr1,r30	# spr25
#	mtspr	spr_dar,r30		# spr19
#	mtspr	spr_dsisr,r30	# spr18

	mtspr	spr_srr0,r30	# spr26
	mtspr	spr_srr1,r30	# spr27

	mtspr	spr_sprg0,r30	# spr272
	mtspr	spr_sprg1,r30	# spr273
	mtspr	spr_sprg2,r30	# spr274
	mtspr	spr_sprg3,r30	# spr275

	# Step 6)  Provide default settings processor specific registers
	#
	mfspr	r3,spr_pvr
	rlwinm	r3,r3,16,16,31

	cmpli	cr0,0,r3,PVR_602
	bc		12,2,init_spr_602	# beq

	cmpli	cr0,0,r3,PVR_603
	bc		12,2,init_spr_603	# beq

	cmpli	cr0,0,r3,PVR_603E
	bc		12,2,init_spr_603E	# beq

	cmpli	cr0,0,r3,PVR_603EV
	bc		12,2,init_spr_603EV	# beq

	cmpli	cr0,0,r3,PVR_604
	bc		12,2,init_spr_604	# beq

	cmpli	cr0,0,r3,PVR_604E
	bc		12,2,init_spr_604E	# beq

	cmpli	cr0,0,r3,PVR_MACH5
	bc		12,2,init_spr_604E	# beq

	cmpli	cr0,0,r3,PVR_750
	bc		12,2,init_spr_750	# beq

	b		init_spr_done

init_spr_602:
	b		init_spr_done

init_spr_603:
init_spr_603E:
init_spr_603EV:
	mtspr	spr_603_dmiss,r30
	mtspr	spr_603_dcmp,r30
	mtspr	spr_603_imiss,r30
	mtspr	spr_603_icmp,r30
	mtspr	spr_603_rpa,r30
	mtspr	spr_603_iabr,r30
	mtspr	spr_603_ear,r30
	b		init_spr_done

init_spr_604:
#	mtspr	spr_604_pmc1,r30
#	mtspr	spr_604_pmc2,r30
	mtspr	spr_604_mmcr0,r30
	mtspr	spr_604_iabr,r30
	mtspr	spr_604_ear,r30
	mfspr	r3,spr_604_hid0
	ori		r3,r3,0x0080			# HID0[SIED]
	mtspr	spr_604_hid0,r3
	isync
	b		init_spr_done

init_spr_604E:
init_spr_MACH5:
#	mtspr	spr_604e_pmc1,r30
#	mtspr	spr_604e_pmc2,r30
#	mtspr	spr_604e_pmc3,r30
#	mtspr	spr_604e_pmc4,r30
	mtspr	spr_604e_mmcr0,r30
	mtspr	spr_604e_mmcr1,r30
	mtspr	spr_604e_iabr,r30
#	mtspr	spr_604e_ear,r30
	mfspr	r3,spr_604e_hid0
	ori		r3,r3,0x0080			# HID0[SIED]
	mtspr	spr_604e_hid0,r3
	isync
	b		init_spr_done

init_spr_750:
#	mtspr	spr_750_pmc1,r30
#	mtspr	spr_750_pmc2,r30
#	mtspr	spr_750_pmc3,r30
#	mtspr	spr_750_pmc4,r30
	mtspr	spr_750_mmcr0,r30
	mtspr	spr_750_mmcr1,r30
#	mtspr	spr_750_thrm1,r30
#	mtspr	spr_750_thrm2,r30
#	mtspr	spr_750_thrm3,r30
	mtspr	spr_750_ictc,r30
	addis	r29,0,0x0020
	sync
	mtspr	spr_750_l2cr,r30		# L2CR[L2E]=0
	sync
	mtspr	spr_750_l2cr,r29		# L2CR[L2I]=1
	addi	r29,0,0x0001
l2loop:
	mfspr	r28,spr_750_l2cr
	cmpw	r28,r29					# L2CR[L2IP]
	beq		l2loop
	sync
	mtspr	spr_750_l2cr,r30		# L2CR[L2I]=0
	sync
	mtspr	spr_750_iabr,r30
	mtspr	spr_750_dabr,r30
#	mtspr	spr_750_ear,r30
	b		init_spr_done

init_spr_done:
	sync
	isync


	# Step 7)  Initialize memory controller.
	#
	bl	mpc10x_init

	# Step 8)  Switch to known good debugger stack space.  Memory
	# controller initialization had better be successful!!!
	#
	addis	r1,r0,(__SP_INIT-20)@h
	ori		r1,r1,(__SP_INIT-20)@l

	# Step 9)  Execute C entry point -- no return
	#
	addis	r3,r0,(main)@h
	ori		r3,r3,(main)@l
	mtspr	LR,r3
	blr						# branch to C main()


######################################################################

#
# When this function is invoked from the exception handler headers
# above, the following is true:
#
# sprg0	 == r31
# sprg1	 == LR
# LR[16-23] == exception number
#
# This routine then saves the entire context and invokes the C
# exception handler.
#
# At an exception, address and data translation are turned off
# MSR[IR,DR] = 0,0.
#
	.equ	MSR_E_MASK,0x87C0FFFF

asm_exception_body:

	# Point r31 to the user register data structure
	addis	r31,r0,(context)@h
	ori		r31,r31,(context)@l

	# Store all GPRs.
	stw		r0,o_r0(r31)		# store r0
	stw		r1,o_r1(r31)		# store r1
	stw		r2,o_r2(r31)		# store r2
	stw		r3,o_r3(r31)		# store r3
	stw		r4,o_r4(r31)		# store r4
	stw		r5,o_r5(r31)		# store r5
	stw		r6,o_r6(r31)		# store r6
	stw		r7,o_r7(r31)		# store r7
	stw		r8,o_r8(r31)		# store r8
	stw		r9,o_r9(r31)		# store r9
	stw		r10,o_r10(r31)		# store r10
	stw		r11,o_r11(r31)		# store r11
	stw		r12,o_r12(r31)		# store r12
	stw		r13,o_r13(r31)		# store r13
	stw		r14,o_r14(r31)		# store r14
	stw		r15,o_r15(r31)		# store r15
	stw		r16,o_r16(r31)		# store r16
	stw		r17,o_r17(r31)		# store r17
	stw		r18,o_r18(r31)		# store r18
	stw		r19,o_r19(r31)		# store r19
	stw		r20,o_r20(r31)		# store r20
	stw		r21,o_r21(r31)		# store r21
	stw		r22,o_r22(r31)		# store r22
	stw		r23,o_r23(r31)		# store r23
	stw		r24,o_r24(r31)		# store r24
	stw		r25,o_r25(r31)		# store r25
	stw		r26,o_r26(r31)		# store r26
	stw		r27,o_r27(r31)		# store r27
	stw		r28,o_r28(r31)		# store r28
	stw		r29,o_r29(r31)		# store r29
	stw		r30,o_r30(r31)		# store r30
	mfspr	r10,spr_sprg0		# r31 at exception (asm_exception_head)
	stw		r10,o_r31(r31)		# store r31
	sync
	isync

#	mfcr	r11
#	stw		r11,o_cr(r31)
#	sync

	# Zero r0
	addis	r0,0,0

	# Reconstruct MSR -- !!! Do I really want to reconstruct???
	addis	r10,r0,(MSR_E_MASK)@h
	ori		r10,r10,(MSR_E_MASK)@l
	mfspr	r11,spr_srr1
	and		r11,r10,r11

	addis	r12,r0,(~MSR_E_MASK)@h
	ori		r12,r12,(~MSR_E_MASK)@l
	mfmsr	r13
	isync
	and		r13,r12,r13

	or		r10,r11,r13

	# Save MSR, CR, IP, XER, LR, CTR
	mfcr	r11
	mfspr	r12,spr_srr0
	mfspr	r13,spr_xer
	mfspr	r14,spr_sprg1	# lr at exception (asm_exception_head)
	mfspr	r15,spr_ctr
	stw		r10,o_msr(r31)
	stw		r11,o_cr(r31)
	stw		r12,o_srr0(r31)
	stw		r13,o_xer(r31)
	stw		r14,o_lr(r31)
	stw		r15,o_ctr(r31)
	sync

	# Save LR before calling routines (LR contains exception number)
	# (Once LR saved, it is okay to use subroutine calls)
	#
	mfspr	r30,spr_lr
	mtspr	spr_sprg1,r30	# LR from bl in asm_exception_head

	#
	# Change the MSR to suit the needs ot the debugger.
	# No interrupts, tracing, address or data translations.
	#
	.equ	DBUG_MSR,0x00001002
	addis	r30,r0,(DBUG_MSR)@h
	ori		r30,r30,(DBUG_MSR)@l
	mtmsr	r30
	isync


	# Store Floating Point registers
	mfmsr	r4
	isync
	addi	r3,r4,0x2000	# MSR[FP]=1
	mtmsr	r3
	sync

	stfd	f0,o_f0(r31)
	mffs	f0
	stfd	f0,o_fpscr(r31)
	stfd	f1,o_f1(r31)
	stfd	f2,o_f2(r31)
	stfd	f3,o_f3(r31)
	stfd	f4,o_f4(r31)
	stfd	f5,o_f5(r31)
	stfd	f6,o_f6(r31)
	stfd	f7,o_f7(r31)
	stfd	f8,o_f8(r31)
	stfd	f9,o_f9(r31)
	stfd	f10,o_f10(r31)
	stfd	f11,o_f11(r31)
	stfd	f12,o_f12(r31)
	stfd	f13,o_f13(r31)
	stfd	f14,o_f14(r31)
	stfd	f15,o_f15(r31)
	stfd	f16,o_f16(r31)
	stfd	f17,o_f17(r31)
	stfd	f18,o_f18(r31)
	stfd	f19,o_f19(r31)
	stfd	f20,o_f20(r31)
	stfd	f21,o_f21(r31)
	stfd	f22,o_f22(r31)
	stfd	f23,o_f23(r31)
	stfd	f24,o_f24(r31)
	stfd	f25,o_f25(r31)
	stfd	f26,o_f26(r31)
	stfd	f27,o_f27(r31)
	stfd	f28,o_f28(r31)
	stfd	f29,o_f29(r31)
	stfd	f30,o_f30(r31)
	stfd	f31,o_f31(r31)
	mtmsr	r4				# MSR[FP]=0
	sync

	# Store all segment registers
	mfsr	r10,sr0
	mfsr	r11,sr1
	mfsr	r12,sr2
	mfsr	r13,sr3
	mfsr	r14,sr4
	mfsr	r15,sr5
	mfsr	r16,sr6
	mfsr	r17,sr7
	mfsr	r18,sr8
	mfsr	r19,sr9
	mfsr	r20,sr10
	mfsr	r21,sr11
	mfsr	r22,sr12
	mfsr	r23,sr13
	mfsr	r24,sr14
	mfsr	r25,sr15
	stw		r10,o_sr0(r31)		# store sr0
	stw		r11,o_sr1(r31)		# store sr1
	stw		r12,o_sr2(r31)		# store sr2
	stw		r13,o_sr3(r31)		# store sr3
	stw		r14,o_sr4(r31)		# store sr4
	stw		r15,o_sr5(r31)		# store sr5
	stw		r16,o_sr6(r31)		# store sr6
	stw		r17,o_sr7(r31)		# store sr7
	stw		r18,o_sr8(r31)		# store sr8
	stw		r19,o_sr9(r31)		# store sr9
	stw		r20,o_sr10(r31)		# store sr10
	stw		r21,o_sr11(r31)		# store sr11
	stw		r22,o_sr12(r31)		# store sr12
	stw		r23,o_sr13(r31)		# store sr13
	stw		r24,o_sr14(r31)		# store sr14
	stw		r25,o_sr15(r31)		# store sr15

	#
	# Store the Special Purpose Registers
	#

tbloop:
	mftb	r14,269			# TBU
	mftb	r13,268			# TBL
	mftb	r15,269			# TBU
	cmpw	r15,r14
	bne		tbloop

	mfspr	r15,spr_pvr
	stw		r13,o_tbl(r31)
	stw		r14,o_tbu(r31)
	stw		r15,o_pvr(r31)
	sync

	mfspr	r10,spr_ibat0u
	mfspr	r11,spr_ibat0l
	mfspr	r12,spr_ibat1u
	mfspr	r13,spr_ibat1l
	mfspr	r14,spr_ibat2u
	mfspr	r15,spr_ibat2l
	mfspr	r16,spr_ibat3u
	mfspr	r17,spr_ibat3l
	stw		r10,o_ibat0u(r31)
	stw		r11,o_ibat0l(r31)
	stw		r12,o_ibat1u(r31)
	stw		r13,o_ibat1l(r31)
	stw		r14,o_ibat2u(r31)
	stw		r15,o_ibat2l(r31)
	stw		r16,o_ibat3u(r31)
	stw		r17,o_ibat3l(r31)
	sync

	mfspr	r10,spr_dbat0u
	mfspr	r11,spr_dbat0l
	mfspr	r12,spr_dbat1u
	mfspr	r13,spr_dbat1l
	mfspr	r14,spr_dbat2u
	mfspr	r15,spr_dbat2l
	mfspr	r16,spr_dbat3u
	mfspr	r17,spr_dbat3l
	stw		r10,o_dbat0u(r31)
	stw		r11,o_dbat0l(r31)
	stw		r12,o_dbat1u(r31)
	stw		r13,o_dbat1l(r31)
	stw		r14,o_dbat2u(r31)
	stw		r15,o_dbat2l(r31)
	stw		r16,o_dbat3u(r31)
	stw		r17,o_dbat3l(r31)
	sync

	mfspr	r10,spr_sdr1
	mfspr	r11,spr_dar
	mfspr	r12,spr_dsisr
	mfspr	r13,spr_dec
	mfspr	r14,spr_srr1
	mfspr	r15,spr_sprg0
	mfspr	r16,spr_sprg1
	mfspr	r17,spr_sprg2
	mfspr	r18,spr_sprg3
	stw		r10,o_sdr1(r31)
	stw		r11,o_dar(r31)
	stw		r12,o_dsisr(r31)
	stw		r13,o_dec(r31)
	stw		r14,o_srr1(r31)
#	stw		r15,o_sprg0(r31)
#	stw		r16,o_sprg1(r31)
	stw		r17,o_sprg2(r31)
	stw		r18,o_sprg3(r31)
	sync

	#
	# Processor specific registers
	#
	mfspr	r3,spr_pvr
	rlwinm	r3,r3,16,16,31

	cmpli	cr0,0,r3,PVR_602
	bc		12,2,save_spr_602	# beq

	cmpli	cr0,0,r3,PVR_603
	bc		12,2,save_spr_603	# beq

	cmpli	cr0,0,r3,PVR_603E
	bc		12,2,save_spr_603E	# beq

	cmpli	cr0,0,r3,PVR_603EV
	bc		12,2,save_spr_603EV	# beq

	cmpli	cr0,0,r3,PVR_604
	bc		12,2,save_spr_604	# beq

	cmpli	cr0,0,r3,PVR_604E
	bc		12,2,save_spr_604E	# beq

	cmpli	cr0,0,r3,PVR_MACH5
	bc		12,2,save_spr_MACH5	# beq

	cmpli	cr0,0,r3,PVR_750
	bc		12,2,save_spr_750	# beq

	b		save_spr_done

	#
	# NOTE:  In the mpc60x.h, the processor specific registers
	# are stored in a C union.  Therefore, the offsets for each
	# of the various registers are probably different.  Ie.
	# the MPC603 and MPC603E both have DMISS, but the actual offset
	# for storing DMISS is not the same.
	#
	# Bottom line, do not share code here unless the processor's
	# union is the same/identical in mpc60x.h
	#
save_spr_602:
	b		save_spr_done

save_spr_603:
	mfspr	r10,spr_603_hid0
	mfspr	r11,spr_603_dmiss
	mfspr	r12,spr_603_dcmp
	mfspr	r13,spr_603_hash1
	mfspr	r14,spr_603_hash2
	mfspr	r15,spr_603_imiss
	mfspr	r16,spr_603_icmp
	mfspr	r17,spr_603_rpa
	mfspr	r18,spr_603_iabr
#	mfspr	r19,spr_603_ear
	stw		r10,o_603_hid0(r31)
	stw		r11,o_603_dmiss(r31)
	stw		r12,o_603_dcmp(r31)
	stw		r13,o_603_hash1(r31)
	stw		r14,o_603_hash2(r31)
	stw		r15,o_603_imiss(r31)
	stw		r16,o_603_icmp(r31)
	stw		r17,o_603_rpa(r31)
	stw		r18,o_603_iabr(r31)
#	stw		r19,o_603_ear(r31)
	mtspr	spr_603_iabr,r0			# disable
	b		save_spr_done

save_spr_603E:
save_spr_603EV:
	mfspr	r10,spr_603e_hid0
	mfspr	r11,spr_603e_hid1
	mfspr	r12,spr_603e_dmiss
	mfspr	r13,spr_603e_dcmp
	mfspr	r14,spr_603e_hash1
	mfspr	r15,spr_603e_hash2
	mfspr	r16,spr_603e_imiss
	mfspr	r17,spr_603e_icmp
	mfspr	r18,spr_603e_rpa
	mfspr	r19,spr_603e_iabr
#	mfspr	r20,spr_603e_ear
	stw		r10,o_603e_hid0(r31)
	stw		r11,o_603e_hid1(r31)
	stw		r12,o_603e_dmiss(r31)
	stw		r13,o_603e_dcmp(r31)
	stw		r14,o_603e_hash1(r31)
	stw		r15,o_603e_hash2(r31)
	stw		r16,o_603e_imiss(r31)
	stw		r17,o_603e_icmp(r31)
	stw		r18,o_603e_rpa(r31)
	stw		r19,o_603e_iabr(r31)
#	stw		r20,o_603e_ear(r31)
	mtspr	spr_603e_iabr,r0			# disable
	b		save_spr_done

save_spr_604:
	mfspr	r10,spr_604_hid0
	mfspr	r11,spr_604_pmc1
	mfspr	r12,spr_604_pmc2
	mfspr	r13,spr_604_mmcr0
	mfspr	r14,spr_604_sda
	mfspr	r15,spr_604_sia
	mfspr	r16,spr_604_iabr
	mfspr	r17,spr_604_dabr
#	mfspr	r18,spr_604_ear
	mfspr	r19,spr_604_pir
	stw		r10,o_604_hid0(r31)
	stw		r11,o_604_pmc1(r31)
	stw		r12,o_604_pmc2(r31)
	stw		r13,o_604_mmcr0(r31)
	stw		r14,o_604_sda(r31)
	stw		r15,o_604_sia(r31)
	stw		r16,o_604_iabr(r31)
	stw		r17,o_604_dabr(r31)
#	stw		r18,o_604_ear(r31)
	stw		r19,o_604_pir(r31)
	mtspr	spr_604_iabr,r0			# disable
	b		save_spr_done

save_spr_604E:
save_spr_MACH5:
	mfspr	r10,spr_604e_hid0
	mfspr	r11,spr_604e_hid1
	mfspr	r12,spr_604e_pmc1
	mfspr	r13,spr_604e_pmc2
	mfspr	r14,spr_604e_pmc3
	mfspr	r15,spr_604e_pmc4
	mfspr	r16,spr_604e_mmcr0
	mfspr	r17,spr_604e_mmcr1
	mfspr	r18,spr_604e_sda
	mfspr	r19,spr_604e_sia
	mfspr	r20,spr_604e_iabr
	mfspr	r21,spr_604e_dabr
#	mfspr	r22,spr_604e_ear
	mfspr	r23,spr_604e_pir
	stw		r10,o_604e_hid0(r31)
	stw		r11,o_604e_hid1(r31)
	stw		r12,o_604e_pmc1(r31)
	stw		r13,o_604e_pmc2(r31)
	stw		r14,o_604e_pmc3(r31)
	stw		r15,o_604e_pmc4(r31)
	stw		r16,o_604e_mmcr0(r31)
	stw		r17,o_604e_mmcr1(r31)
	stw		r18,o_604e_sda(r31)
	stw		r19,o_604e_sia(r31)
	stw		r20,o_604e_iabr(r31)
	stw		r21,o_604e_dabr(r31)
#	stw		r22,o_604e_ear(r31)
	stw		r23,o_604e_pir(r31)
	mtspr	spr_604e_iabr,r0			# disable
	b		save_spr_done

save_spr_750:
#	mfspr	r5,spr_750_upmc1
#	mfspr	r6,spr_750_upmc2
#	mfspr	r7,spr_750_upmc3
#	mfspr	r8,spr_750_upmc4
#	mfspr	r9,spr_750_usia
#	mfspr	r10,spr_750_ummcr0
#	mfspr	r11,spr_750_ummcr1
#	mfspr	r12,spr_750_hid0
#	mfspr	r13,spr_750_hid1
#	mfspr	r14,spr_750_pmc1
#	mfspr	r15,spr_750_pmc2
#	mfspr	r16,spr_750_pmc3
#	mfspr	r17,spr_750_pmc4
#	mfspr	r18,spr_750_mmcr0
#	mfspr	r19,spr_750_mmcr1
#	mfspr	r20,spr_750_sia
#	mfspr	r21,spr_750_thrm1
#	mfspr	r22,spr_750_thrm2
#	mfspr	r23,spr_750_thrm3
#	mfspr	r24,spr_750_ictc
#	mfspr	r25,spr_750_l2cr
#	mfspr	r26,spr_750_iabr
#	mfspr	r27,spr_750_dabr
#	mfspr	r28,spr_750_ear
	stw		r5,o_750_upmc1(r31)
	stw		r6,o_750_upmc2(r31)
	stw		r7,o_750_upmc3(r31)
	stw		r8,o_750_upmc4(r31)
	stw		r9,o_750_usia(r31)
	stw		r10,o_750_ummcr0(r31)
	stw		r11,o_750_ummcr1(r31)
	stw		r12,o_750_hid0(r31)
	stw		r13,o_750_hid1(r31)
	stw		r14,o_750_pmc1(r31)
	stw		r15,o_750_pmc2(r31)
	stw		r16,o_750_pmc3(r31)
	stw		r17,o_750_pmc4(r31)
	stw		r18,o_750_mmcr0(r31)
	stw		r19,o_750_mmcr1(r31)
	stw		r20,o_750_sia(r31)
#	stw		r21,o_750_thrm1(r31)
#	stw		r22,o_750_thrm2(r31)
#	stw		r23,o_750_thrm3(r31)
	stw		r24,o_750_ictc(r31)
	stw		r25,o_750_l2cr(r31)
	stw		r26,o_750_iabr(r31)
	stw		r27,o_750_dabr(r31)
#	stw		r28,o_750_ear(r31)
	mtspr	spr_750_iabr,r0			# disable
	b		save_spr_done


save_spr_done:
	sync
	isync

	#
	# Context save complete!  Change to monitor stack and make
	# memory coherent.  Because the caches use physical addresses
	# (versus logical addresses) for tags, no issues with coherency
	# between a possible virtual environment and the simple environment
	# that the debugger executes in.
	#

	addis	r1,r0,(__SP_INIT-20)@h
	ori		r1,r1,(__SP_INIT-20)@l

	bl		cpu_cache_flush
	bl		mpc10x_l2_flush

	# Invoke the C exception handler.
	#
	# int cpu_handler (ADDRESS exception);
	#
	mfspr	r3,spr_sprg1		# the address in LR indicates exception
	bl		cpu_handler

	# Code to determine if we go back to monitor or user code
	# r3 == 1 if to go back to monitor, 0 for RFI
	cmpi	cr0,0,r3,0x0001
	beq		cr0,backtomonitor

	# restore state and execute rfi.
	# Point r3 to the user register data structure
	addis	r3,r0,(context)@h
	ori		r3,r3,(context)@l
	b		asm_switch_context

	# The RFI is performed in asm_switch_context

backtomonitor:
	b		mainloop


######################################################################

#
# This routine is called from a system call to save the context and
# return to the dBUG prompt.  This routine is used in conjuction with
# asm_exception_body() and cpu_handler() to avoid rewriting/copying
# the context save code.  It passes exception #0xFF00 to cpu_handler(),
# which will then dump out to the dBUG prompt.
#
# Prior to invoking this routine, the caller must have ensured that
# the entry conditions for asm_exception_body have already been met,
# with the exception that LR is set here to indicate bogus exception.
#

asm_sc_exit_to_dbug:
	addi	r31,0,-1
	mtspr	spr_lr,r31
	b		asm_exception_body


######################################################################

#