mpc6xx_lo.s

Coldfire MCF5282 DBug bootloader

	#
	# File:		mpc6xx_lo.s
	#
	# Purpose:	Low level routines for all MPC6XX dBUG
	#
	# Notes:	This file assembles with both Diab and GNU assemblers
	#
	# Author:	Eric DeVolder
	# Date:
	#
	# Modificiations:
	#
	#

######################################################################

	.equ	PVR_602,0x0002
	.equ	PVR_603,0x0003
	.equ	PVR_604,0x0004
	.equ	PVR_603E,0x0006
	.equ	PVR_603EV,0x0007
	.equ	PVR_750,0x0008
	.equ	PVR_604E,0x0009
	.equ	PVR_MACH5,0x000A
	.equ	PVR_620,0x0014

######################################################################

	# Globally accessible symbols
	.extern VECTOR_TABLE

	.global asm_startmeup			# Called by dBUG reset command
	.global asm_exception_body
	.global asm_isr_handler
	.global asm_switch_context
	.global asm_sc_exit_to_dbug

	.global cpu_iord_8
	.global cpu_iord_16
	.global cpu_iord_32
	.global cpu_iowr_8
	.global cpu_iowr_16
	.global cpu_iowr_32

	.global cpu_iord_16r				# byte reversed
	.global cpu_iord_32r
	.global cpu_iowr_16r
	.global cpu_iowr_32r

	.global cpu_cache_flush

	.global mpc6xx_wr_msr
	.global mpc6xx_rd_msr

	.global mpc6xx_wr_sr0
	.global mpc6xx_rd_sr0
	.global mpc6xx_wr_sr1
	.global mpc6xx_rd_sr1
	.global mpc6xx_wr_sr2
	.global mpc6xx_rd_sr2
	.global mpc6xx_wr_sr3
	.global mpc6xx_rd_sr3
	.global mpc6xx_wr_sr4
	.global mpc6xx_rd_sr4
	.global mpc6xx_wr_sr5
	.global mpc6xx_rd_sr5
	.global mpc6xx_wr_sr6
	.global mpc6xx_rd_sr6
	.global mpc6xx_wr_sr7
	.global mpc6xx_rd_sr7
	.global mpc6xx_wr_sr8
	.global mpc6xx_rd_sr8
	.global mpc6xx_wr_sr9
	.global mpc6xx_rd_sr9
	.global mpc6xx_wr_sr10
	.global mpc6xx_rd_sr10
	.global mpc6xx_wr_sr11
	.global mpc6xx_rd_sr11
	.global mpc6xx_wr_sr12
	.global mpc6xx_rd_sr12
	.global mpc6xx_wr_sr13
	.global mpc6xx_rd_sr13
	.global mpc6xx_wr_sr14
	.global mpc6xx_rd_sr14
	.global mpc6xx_wr_sr15
	.global mpc6xx_rd_sr15

	.global mpc6xx_wr_tbl
	.global mpc6xx_rd_tbl
	.global mpc6xx_wr_tbu
	.global mpc6xx_rd_tbu

	.global mpc6xx_rd_pvr

	.global mpc6xx_wr_ibat0u
	.global mpc6xx_rd_ibat0u
	.global mpc6xx_wr_ibat0l
	.global mpc6xx_rd_ibat0l
	.global mpc6xx_wr_ibat1u
	.global mpc6xx_rd_ibat1u
	.global mpc6xx_wr_ibat1l
	.global mpc6xx_rd_ibat1l
	.global mpc6xx_wr_ibat2u
	.global mpc6xx_rd_ibat2u
	.global mpc6xx_wr_ibat2l
	.global mpc6xx_rd_ibat2l
	.global mpc6xx_wr_ibat3u
	.global mpc6xx_rd_ibat3u
	.global mpc6xx_wr_ibat3l
	.global mpc6xx_rd_ibat3l

	.global mpc6xx_wr_dbat0u
	.global mpc6xx_rd_dbat0u
	.global mpc6xx_wr_dbat0l
	.global mpc6xx_rd_dbat0l
	.global mpc6xx_wr_dbat1u
	.global mpc6xx_rd_dbat1u
	.global mpc6xx_wr_dbat1l
	.global mpc6xx_rd_dbat1l
	.global mpc6xx_wr_dbat2u
	.global mpc6xx_rd_dbat2u
	.global mpc6xx_wr_dbat2l
	.global mpc6xx_rd_dbat2l
	.global mpc6xx_wr_dbat3u
	.global mpc6xx_rd_dbat3u
	.global mpc6xx_wr_dbat3l
	.global mpc6xx_rd_dbat3l

	.global mpc6xx_wr_sdr1
	.global mpc6xx_rd_sdr1

	.global mpc6xx_wr_dar
	.global mpc6xx_rd_dar

	.global mpc6xx_wr_dsisr
	.global mpc6xx_rd_dsisr

	.global mpc6xx_wr_dec
	.global mpc6xx_rd_dec

	.global mpc603_wr_hid0
	.global mpc603_rd_hid0
	.global mpc603_wr_dmiss
	.global mpc603_rd_dmiss
	.global mpc603_wr_dcmp
	.global mpc603_rd_dcmp
	.global mpc603_rd_hash1
	.global mpc603_rd_hash2
	.global mpc603_wr_imiss
	.global mpc603_rd_imiss
	.global mpc603_wr_icmp
	.global mpc603_rd_icmp
	.global mpc603_wr_rpa
	.global mpc603_rd_rpa
	.global mpc603_wr_iabr
	.global mpc603_rd_iabr
	.global mpc603_wr_ear
	.global mpc603_rd_ear

	.global mpc603e_wr_hid0
	.global mpc603e_rd_hid0
	.global mpc603e_wr_hid1
	.global mpc603e_rd_hid1
	.global mpc603e_wr_dmiss
	.global mpc603e_rd_dmiss
	.global mpc603e_wr_dcmp
	.global mpc603e_rd_dcmp
	.global mpc603e_rd_hash1
	.global mpc603e_rd_hash2
	.global mpc603e_wr_imiss
	.global mpc603e_rd_imiss
	.global mpc603e_wr_icmp
	.global mpc603e_rd_icmp
	.global mpc603e_wr_rpa
	.global mpc603e_rd_rpa
	.global mpc603e_wr_iabr
	.global mpc603e_rd_iabr
	.global mpc603e_wr_ear
	.global mpc603e_rd_ear

	.global mpc604_wr_hid0
	.global mpc604_rd_hid0
	.global mpc604_rd_pmc1
	.global mpc604_rd_pmc2
	.global mpc604_wr_mmcr0
	.global mpc604_rd_mmcr0
	.global mpc604_rd_sda
	.global mpc604_rd_sia
	.global mpc604_wr_iabr
	.global mpc604_rd_iabr
	.global mpc604_wr_dabr
	.global mpc604_rd_dabr
	.global mpc604_wr_ear
	.global mpc604_rd_ear
	.global mpc604_rd_pir

	.global mpc604e_wr_hid0
	.global mpc604e_rd_hid0
	.global mpc604e_rd_hid1
	.global mpc604e_rd_pmc1
	.global mpc604e_rd_pmc2
	.global mpc604e_wr_mmcr0
	.global mpc604e_rd_mmcr0
	.global mpc604e_rd_sda
	.global mpc604e_rd_sia
	.global mpc604e_wr_iabr
	.global mpc604e_rd_iabr
	.global mpc604e_wr_dabr
	.global mpc604e_rd_dabr
	.global mpc604e_wr_ear
	.global mpc604e_rd_ear
	.global mpc604e_rd_pir

	.global mpc750_rd_upmc1
	.global mpc750_rd_upmc2
	.global mpc750_rd_upmc3
	.global mpc750_rd_upmc4
	.global mpc750_rd_usia
	.global mpc750_rd_ummcr0
	.global mpc750_rd_ummcr1
	.global mpc750_wr_hid0
	.global mpc750_rd_hid0
	.global mpc750_rd_hid1
	.global mpc750_rd_pmc1
	.global mpc750_rd_pmc2
	.global mpc750_rd_pmc3
	.global mpc750_rd_pmc4
	.global mpc750_wr_mmcr0
	.global mpc750_rd_mmcr0
	.global mpc750_wr_mmcr1
	.global mpc750_rd_mmcr1
	.global mpc750_rd_sia
	.global mpc750_wr_thrm1
	.global mpc750_rd_thrm1
	.global mpc750_wr_thrm2
	.global mpc750_rd_thrm2
	.global mpc750_wr_thrm3
	.global mpc750_rd_thrm3
	.global mpc750_wr_ictc
	.global mpc750_rd_ictc
	.global mpc750_wr_l2cr
	.global mpc750_rd_l2cr
	.global mpc750_wr_iabr
	.global mpc750_rd_iabr
	.global mpc750_wr_dabr
	.global mpc750_rd_dabr
	.global mpc750_wr_ear
	.global mpc750_rd_ear


######################################################################
######################################################################
######################################################################

	.equ	sr0,0
	.equ	sr1,1
	.equ	sr2,2
	.equ	sr3,3
	.equ	sr4,4
	.equ	sr5,5
	.equ	sr6,6
	.equ	sr7,7
	.equ	sr8,8
	.equ	sr9,9
	.equ	sr10,10
	.equ	sr11,11
	.equ	sr12,12
	.equ	sr13,13
	.equ	sr14,14
	.equ	sr15,15

	#
	# Offsets of registers in the REGISTERS data structure.
	# NOTE:  Offsets must match compiler calculated offsets!
	#

	.equ	o_r0,000000
	.equ	o_r1,0x0004
	.equ	o_r2,0x0008
	.equ	o_r3,0x000c
	.equ	o_r4,0x0010
	.equ	o_r5,0x0014
	.equ	o_r6,0x0018
	.equ	o_r7,0x001c
	.equ	o_r8,0x0020
	.equ	o_r9,0x0024
	.equ	o_r10,0x0028
	.equ	o_r11,0x002c
	.equ	o_r12,0x0030
	.equ	o_r13,0x0034
	.equ	o_r14,0x0038
	.equ	o_r15,0x003c
	.equ	o_r16,0x0040
	.equ	o_r17,0x0044
	.equ	o_r18,0x0048
	.equ	o_r19,0x004c
	.equ	o_r20,0x0050
	.equ	o_r21,0x0054
	.equ	o_r22,0x0058
	.equ	o_r23,0x005c
	.equ	o_r24,0x0060
	.equ	o_r25,0x0064
	.equ	o_r26,0x0068
	.equ	o_r27,0x006c
	.equ	o_r28,0x0070
	.equ	o_r29,0x0074
	.equ	o_r30,0x0078
	.equ	o_r31,0x007c
	.equ	o_f0,0x0080
	.equ	o_f1,0x0088
	.equ	o_f2,0x0090
	.equ	o_f3,0x0098
	.equ	o_f4,0x00a0
	.equ	o_f5,0x00a8
	.equ	o_f6,0x00b0
	.equ	o_f7,0x00b8
	.equ	o_f8,0x00c0
	.equ	o_f9,0x00c8
	.equ	o_f10,0x00d0
	.equ	o_f11,0x00d8
	.equ	o_f12,0x00e0
	.equ	o_f13,0x00e8
	.equ	o_f14,0x00f0
	.equ	o_f15,0x00f8
	.equ	o_f16,0x0100
	.equ	o_f17,0x0108
	.equ	o_f18,0x0110
	.equ	o_f19,0x0118
	.equ	o_f20,0x0120
	.equ	o_f21,0x0128
	.equ	o_f22,0x0130
	.equ	o_f23,0x0138
	.equ	o_f24,0x0140
	.equ	o_f25,0x0148
	.equ	o_f26,0x0150
	.equ	o_f27,0x0158
	.equ	o_f28,0x0160
	.equ	o_f29,0x0168
	.equ	o_f30,0x0170
	.equ	o_f31,0x0178
	.equ	o_cr,0x0180
	.equ	o_fpscr,0x0184
	.equ	o_xer,0x0188
	.equ	o_lr,0x018c
	.equ	o_ctr,0x0190
	.equ	o_tbl,0x0194
	.equ	o_tbu,0x0198
	.equ	o_msr,0x019c
	.equ	o_pvr,0x01a0
	.equ	o_ibat0u,0x01a4
	.equ	o_ibat0l,0x01a8
	.equ	o_ibat1u,0x01ac
	.equ	o_ibat1l,0x01b0
	.equ	o_ibat2u,0x01b4
	.equ	o_ibat2l,0x01b8
	.equ	o_ibat3u,0x01bc
	.equ	o_ibat3l,0x01c0
	.equ	o_dbat0u,0x01c4
	.equ	o_dbat0l,0x01c8
	.equ	o_dbat1u,0x01cc
	.equ	o_dbat1l,0x01d0
	.equ	o_dbat2u,0x01d4
	.equ	o_dbat2l,0x01d8
	.equ	o_dbat3u,0x01dc
	.equ	o_dbat3l,0x01e0
	.equ	o_sr0,0x01e4
	.equ	o_sr1,0x01e8
	.equ	o_sr2,0x01ec
	.equ	o_sr3,0x01f0
	.equ	o_sr4,0x01f4
	.equ	o_sr5,0x01f8
	.equ	o_sr6,0x01fc
	.equ	o_sr7,0x0200
	.equ	o_sr8,0x0204
	.equ	o_sr9,0x0208
	.equ	o_sr10,0x020c
	.equ	o_sr11,0x0210
	.equ	o_sr12,0x0214
	.equ	o_sr13,0x0218
	.equ	o_sr14,0x021c
	.equ	o_sr15,0x0220
	.equ	o_sdr1,0x0224
	.equ	o_dar,0x0228
	.equ	o_dsisr,0x022c
	.equ	o_srr0,0x0230
	.equ	o_srr1,0x0234
	.equ	o_sprg0,0x0238
	.equ	o_sprg1,0x023c
	.equ	o_sprg2,0x0240
	.equ	o_sprg3,0x0244
	.equ	o_dec,0x0248
	.equ	o_603_hid0,0x024c
	.equ	o_603_dmiss,0x0250
	.equ	o_603_dcmp,0x0254
	.equ	o_603_hash1,0x0258
	.equ	o_603_hash2,0x025c
	.equ	o_603_imiss,0x0260
	.equ	o_603_icmp,0x0264
	.equ	o_603_rpa,0x0268
	.equ	o_603_iabr,0x026c
	.equ	o_603_ear,0x0270
	.equ	o_603e_hid0,0x024c
	.equ	o_603e_hid1,0x0250
	.equ	o_603e_dmiss,0x0254
	.equ	o_603e_dcmp,0x0258
	.equ	o_603e_hash1,0x025c
	.equ	o_603e_hash2,0x0260
	.equ	o_603e_imiss,0x0264
	.equ	o_603e_icmp,0x0268
	.equ	o_603e_rpa,0x026c
	.equ	o_603e_iabr,0x0270
	.equ	o_603e_ear,0x0274
	.equ	o_604_hid0,0x024c
	.equ	o_604_pmc1,0x0250
	.equ	o_604_pmc2,0x0254
	.equ	o_604_mmcr0,0x0258
	.equ	o_604_sda,0x025c
	.equ	o_604_sia,0x0260
	.equ	o_604_iabr,0x0264
	.equ	o_604_dabr,0x0268
	.equ	o_604_ear,0x026c
	.equ	o_604_pir,0x0270
	.equ	o_604e_hid0,0x024c
	.equ	o_604e_hid1,0x0250
	.equ	o_604e_pmc1,0x0254
	.equ	o_604e_pmc2,0x0258
	.equ	o_604e_pmc3,0x025c
	.equ	o_604e_pmc4,0x0260
	.equ	o_604e_mmcr0,0x0264
	.equ	o_604e_mmcr1,0x0268
	.equ	o_604e_sda,0x026c
	.equ	o_604e_sia,0x0270
	.equ	o_604e_iabr,0x0274
	.equ	o_604e_dabr,0x0278
	.equ	o_604e_ear,0x027c
	.equ	o_604e_pir,0x0280
	.equ	o_750_upmc1,0x024c
	.equ	o_750_upmc2,0x0250
	.equ	o_750_upmc3,0x0254
	.equ	o_750_upmc4,0x0258
	.equ	o_750_usia,0x025c
	.equ	o_750_ummcr0,0x0260
	.equ	o_750_ummcr1,0x0264
	.equ	o_750_hid0,0x0268
	.equ	o_750_hid1,0x026c
	.equ	o_750_pmc1,0x0270
	.equ	o_750_pmc2,0x0274
	.equ	o_750_pmc3,0x0278
	.equ	o_750_pmc4,0x027c
	.equ	o_750_mmcr0,0x0280
	.equ	o_750_mmcr1,0x0284
	.equ	o_750_sia,0x0288
	.equ	o_750_thrm1,0x028c
	.equ	o_750_thrm2,0x0290
	.equ	o_750_thrm3,0x0294
	.equ	o_750_ictc,0x0298
	.equ	o_750_l2cr,0x029c
	.equ	o_750_iabr,0x02a0
	.equ	o_750_dabr,0x02a4
	.equ	o_750_ear,0x02a8


	#
	# PowerPC Special Purpose Register numbers
	#

	.equ	spr_xer,1
	.equ	spr_lr,8
	.equ	spr_ctr,9
	.equ	spr_tbl,268
	.equ	spr_tbu,269
	.equ	spr_pvr,287
	.equ	spr_ibat0u,528
	.equ	spr_ibat0l,529
	.equ	spr_ibat1u,530
	.equ	spr_ibat1l,531
	.equ	spr_ibat2u,532
	.equ	spr_ibat2l,533
	.equ	spr_ibat3u,534
	.equ	spr_ibat3l,535
	.equ	spr_dbat0u,536
	.equ	spr_dbat0l,537
	.equ	spr_dbat1u,538
	.equ	spr_dbat1l,539
	.equ	spr_dbat2u,540
	.equ	spr_dbat2l,541
	.equ	spr_dbat3u,542
	.equ	spr_dbat3l,543
	.equ	spr_sdr1,25
	.equ	spr_dar,19
	.equ	spr_dsisr,18
	.equ	spr_srr0,26
	.equ	spr_srr1,27
	.equ	spr_sprg0,272
	.equ	spr_sprg1,273
	.equ	spr_sprg2,274
	.equ	spr_sprg3,275
	.equ	spr_dec,22
	.equ	spr_603_hid0,1008
	.equ	spr_603_dmiss,976
	.equ	spr_603_dcmp,977
	.equ	spr_603_hash1,978
	.equ	spr_603_hash2,979
	.equ	spr_603_imiss,980
	.equ	spr_603_icmp,981
	.equ	spr_603_rpa,982
	.equ	spr_603_iabr,1010
	.equ	spr_603_ear,282
	.equ	spr_603e_hid0,1008
	.equ	spr_603e_hid1,1009
	.equ	spr_603e_dmiss,976
	.equ	spr_603e_dcmp,977
	.equ	spr_603e_hash1,978
	.equ	spr_603e_hash2,979
	.equ	spr_603e_imiss,980
	.equ	spr_603e_icmp,981
	.equ	spr_603e_rpa,982
	.equ	spr_603e_iabr,1010
	.equ	spr_603e_ear,282
	.equ	spr_604_hid0,1008
	.equ	spr_604_pmc1,953
	.equ	spr_604_pmc2,954
	.equ	spr_604_mmcr0,952
	.equ	spr_604_sda,959
	.equ	spr_604_sia,955
	.equ	spr_604_iabr,1010
	.equ	spr_604_dabr,1013
	.equ	spr_604_ear,282
	.equ	spr_604_pir,1023
	.equ	spr_604e_hid0,1008
	.equ	spr_604e_hid1,1009
	.equ	spr_604e_pmc1,953
	.equ	spr_604e_pmc2,954
	.equ	spr_604e_pmc3,957
	.equ	spr_604e_pmc4,958
	.equ	spr_604e_mmcr0,952
	.equ	spr_604e_mmcr1,956
	.equ	spr_604e_sda,959
	.equ	spr_604e_sia,955
	.equ	spr_604e_iabr,1010
	.equ	spr_604e_dabr,1013
	.equ	spr_604e_ear,282
	.equ	spr_604e_pir,1023
	.equ	spr_750_upmc1,937
	.equ	spr_750_upmc2,938
	.equ	spr_750_upmc3,941
	.equ	spr_750_upmc4,942
	.equ	spr_750_usia,939
	.equ	spr_750_ummcr0,936
	.equ	spr_750_ummcr1,940
	.equ	spr_750_hid0,1008
	.equ	spr_750_hid1,1009
	.equ	spr_750_pmc1,953
	.equ	spr_750_pmc2,954
	.equ	spr_750_pmc3,957
	.equ	spr_750_pmc4,958
	.equ	spr_750_mmcr0,952
	.equ	spr_750_mmcr1,956
	.equ	spr_750_sia,955
	.equ	spr_750_thrm1,1020
	.equ	spr_750_thrm2,1021
	.equ	spr_750_thrm3,1022
	.equ	spr_750_ictc,1019
	.equ	spr_750_l2cr,1017
	.equ	spr_750_iabr,1010
	.equ	spr_750_dabr,1013
	.equ	spr_750_ear,282



######################################################################
######################################################################
######################################################################

	.text
#
# This is the entry point upon reset, or the RESET command.  This
# code assumes that _NO_DRAM_IS_PRESENT_!!!!  This code assumes that
# a memory controller will need software initialization.
#
asm_startmeup:

	# Step 1) Disable FPU, Enable Big-Endian, Supervisor Mode,
	# Disable Interrupts, and I- or D- address translation.
	#
	.equ	HR_MSR,0x00001002
	addis	r31,r0,(HR_MSR)@h
	ori		r31,r31,(HR_MSR)@l
	mtmsr	r31
	isync

	# Step 2) Invalidate the Instruction and Data caches, d-cache disabled
	# Machine check pin enabled HID0[EMCP].
	#
	# MPC602, MPC603, MPC603e, MPC604, MPC604e all have HID0 as
	# spr1008, and all have HID0[EMCP,ICFI,DCFI] in the same
	# bit locations
	#
	.equ	HR_HID0_a,0x00000C00
	.equ	HR_HID0_b,0x80000000
	addis	r31,r0,(HR_HID0_a)@h
	ori		r31,r31,(HR_HID0_a)@l
	addis	r30,r0,(HR_HID0_b)@h
	ori		r30,r30,(HR_HID0_b)@l
	sync
	mtspr	spr_603_hid0,r31		# set invalidate bits
	mtspr	spr_603_hid0,r30		# clear invalidate bits
	isync

	# Step 3) Clear out the TLBs.
	#
	# MPC602, MPC603, MPC603e, MPC604, MPC604e all accept the TLBIE
	# instruction.
	#
	# 128 iterations is sufficient for all current parts, and perhaps
	# a few newer ones?
	#
	addi	r0,0,1
	addi	r3,0,0
	addi	r4,0,0
	sync
tlbloop:
	tlbie	r4
	tlbsync
	addi	r4,r4,0x1000
	add.	r3,r3,r0
	cmpli	cr0,0,r3,128
	bne		tlbloop

	addis	r30,0,0			# Zero r30

	mtcrf	0xFF,r30		# Clear out CRs

	# Step 4) Zero FPU registers
	#
	b		init_fpu
zero_for_fpu:
	#dc.l	0
	.long	0

init_fpu:
	addis	r28,0,(zero_for_fpu)@h
	ori		r28,r28,(zero_for_fpu)@l
	mfmsr	r4
	isync
	addi	r3,r4,0x2000	# MSR[FP]=1
	mtmsr	r3
	sync

	lfd		f0,0(r28)
	lfd		f1,0(r28)
	lfd		f2,0(r28)
	lfd		f3,0(r28)
	lfd		f4,0(r28)
	lfd		f5,0(r28)
	lfd		f6,0(r28)
	lfd		f7,0(r28)
	lfd		f8,0(r28)
	lfd		f9,0(r28)
	lfd		f10,0(r28)
	lfd		f11,0(r28)
	lfd		f12,0(r28)
	lfd		f13,0(r28)
	lfd		f14,0(r28)
	lfd		f15,0(r28)
	lfd		f16,0(r28)
	lfd		f17,0(r28)
	lfd		f18,0(r28)
	lfd		f19,0(r28)
	lfd		f20,0(r28)
	lfd		f21,0(r28)
	lfd		f22,0(r28)
	lfd		f23,0(r28)
	lfd		f24,0(r28)
	lfd		f25,0(r28)
	lfd		f26,0(r28)
	lfd		f27,0(r28)
	lfd		f28,0(r28)
	lfd		f29,0(r28)
	lfd		f30,0(r28)
	lfd		f31,0(r28)

	mtfsfi	0,0
	mtfsfi	1,0
	mtfsfi	2,0
	mtfsfi	3,0
	mtfsfi	4,0
	mtfsfi	5,0
	mtfsfi	6,0
	mtfsfi	7,0
	isync

	mtmsr	r4				# MSR[FP]=0
	sync
	

	# Step 5)  Provide default settings special purpose registers
	#
	mtspr	spr_xer,r30		# spr1
	mtspr	spr_ctr,r30		# spr9

	mtspr	284,r30			# tbl
	mtspr	285,r30			# tbu
	mtspr	284,r30			# tbl
	isync

	mtspr	spr_ibat0u,r30	# spr528
	mtspr	spr_ibat0l,r30	# spr529