mcf5307_lo.s

Coldfire MCF5282 DBug bootloader

/*
 * File:	mcf5307_lo.s
 * Purpose:	Lowest level routines for mcf5307.
 *
 * Notes:	This file assembles with both Diab and GNU tools
 *
 */

#ifdef _UNDERSCORE_
#define mcf5307_init    _mcf5307_init
#define main            _main
#endif
 
	.extern ___MBAR
	.extern ___SRAM
    .extern ___SP_INIT
    .extern mcf5307_init
    .extern main
 
    .global asm_startmeup
    .global _asm_startmeup
    .global asm_execute_user_flash
    .global _asm_execute_user_flash
    .global cpu_cache_flush
    .global _cpu_cache_flush
	.global	_cpu_cache_disable
	.global cpu_cache_disable

	.equ	SRAMsize,4096	/* 4K Byte SRAM */

	.text

/********************************************************************
 * This is the main entry point upon hard reset.
 */
asm_startmeup:
_asm_startmeup:
	
	move.w	#0x2700,sr

	/* Initialize MBAR */
	move.l #(___MBAR + 1),d0
	movec	d0,MBAR
	
	/* Initialize RAMBAR: locate SRAM and validate it */
	move.l	#(___SRAM + 0x21),d0
	movec	d0,RAMBAR

	/* Point Stack Pointer into SRAM temporarily */
	move.l	#(___SRAM + SRAMsize),sp

	/* Initialize mcf5307 periphs, etc */
	jsr		mcf5307_init

	/* Relocate Stack Pointer */ 
	move.l	#___SP_INIT,sp

	/* Jump to the main process */
	jmp		main
	
	bra		.
	nop
	nop
	halt

/*******************************************************************/
_asm_execute_user_flash:
asm_execute_user_flash:
		move.l	8(sp),a0	/* get new PC */
		move.l	4(sp),a7	/* get new SP */
		clr.l	d0			
		movec	d0,VBR		/* reset VBR to reset value */
		jmp	(a0)			/* execute at new PC */

/********************************************************************
 *	Routine to cleanly flush the cache, pushing all lines and 
 *	invalidating them.  This must be done to change the cache when 
 *	we have been operating in copyback mode (i.e. writes to a copyback 
 *	region are probably resident in the cache and not in the main store).
 */
_cpu_cache_flush:
cpu_cache_flush:
	nop					/* synchronize - flush store buffer */

	moveq.l	#0,d0		/* init line counter */
	moveq.l #0,d1		/* init set counter */
	move.l	d0,a0		/* init An */

flushloop:

 	cpushl	(a0)		/* push cache line a0 - GNU Compiler */
/*	cpushl	bc,(a0) */	/* push cache line a0 - Diab Compiler */

	add.l	#0x0010,a0	/* increment setindex by 1 */
	addq.l	#1,d1		/* increment set counter */
	cmpi.l	#128,d1		/* are sets for this line done? */
	bne		flushloop

	moveq.l	#0,d1		/* set counter to zero again */
	addq.l	#1,d0		/* increment to next line */
	move.l	d0,a0		/* set 0, line d0 into a0 as per cpushl */
	cmpi.l	#4,d0
	bne		flushloop

	rts

/********************************************************************
 *	Routine to disable the cache completely
 */
_cpu_cache_disable:
cpu_cache_disable:
	nop
	jsr		_cpu_cache_flush	/* flush the cache completely */	
	clr.l	d0
	movec	d0,ACR0			/* ACR0 off */
	movec	d0,ACR1			/* ACR1 off */
	move.l	#0x01000000,d0	/* Invalidate and disable cache */
	movec	d0,CACR
	rts

	.end