📄 mcf5249.h
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/*
* File: src/include/cpu/coldfire/mcf5249.h
* Purpose: MCF5249 definitions
*
* Notes: This file automatically included.
*
*/
#ifndef _CPU_MCF5249_H
#define _CPU_MCF5249_H
/*********************************************************************
*
* System Configuration Registers (SIM)
*
*********************************************************************/
#define MCF5249_SIM_RSR (*(vuint8 *)(void *)(&__MBAR[0x00]))
#define MCF5249_SIM_SYPCR (*(vuint8 *)(void *)(&__MBAR[0x01]))
#define MCF5249_SIM_SWIVR (*(vuint8 *)(void *)(&__MBAR[0x02]))
#define MCF5249_SIM_SWSR (*(vuint8 *)(void *)(&__MBAR[0x03]))
#define MCF5249_SIM_IRQPAR (*(vuint8 *)(void *)(&__MBAR[0x06]))
#define MCF5249_SIM_MPARK (*(vuint8 *)(void *)(&__MBAR[0x0C]))
#define MCF5249_SIM_IPR (*(vuint32 *)(void *)(&__MBAR[0x40]))
#define MCF5249_SIM_IMR (*(vuint32 *)(void *)(&__MBAR[0x44]))
#define MCF5249_SIM_AVCR (*(vuint8 *)(void *)(&__MBAR[0x51]))
#define MCF5249_SIM_ICR0 (*(vuint8 *)(void *)(&__MBAR[0x4C]))
#define MCF5249_SIM_ICR1 (*(vuint8 *)(void *)(&__MBAR[0x4D]))
#define MCF5249_SIM_ICR2 (*(vuint8 *)(void *)(&__MBAR[0x4E]))
#define MCF5249_SIM_ICR3 (*(vuint8 *)(void *)(&__MBAR[0x4F]))
#define MCF5249_SIM_ICR4 (*(vuint8 *)(void *)(&__MBAR[0x50]))
#define MCF5249_SIM_ICR5 (*(vuint8 *)(void *)(&__MBAR[0x51]))
#define MCF5249_SIM_ICR6 (*(vuint8 *)(void *)(&__MBAR[0x52]))
#define MCF5249_SIM_ICR7 (*(vuint8 *)(void *)(&__MBAR[0x53]))
#define MCF5249_SIM_ICR8 (*(vuint8 *)(void *)(&__MBAR[0x54]))
#define MCF5249_SIM_ICR9 (*(vuint8 *)(void *)(&__MBAR[0x55]))
#define MCF5249_SIM_ICR10 (*(vuint8 *)(void *)(&__MBAR[0x56]))
#define MCF5249_SIM_ICR11 (*(vuint8 *)(void *)(&__MBAR[0x57]))
#define MCF5249_SIM_GPIO_READ (*(vuint32 *)(void *)(&__MBAR2[0x00]))
#define MCF5249_SIM_GPIO_OUT (*(vuint32 *)(void *)(&__MBAR2[0x04]))
#define MCF5249_SIM_GPIO_ENABLE (*(vuint32 *)(void *)(&__MBAR2[0x08]))
#define MCF5249_SIM_GPIO_FUNC (*(vuint32 *)(void *)(&__MBAR2[0x0C]))
#define MCF5249_SIM_DEVID (*(vuint32 *)(void *)(&__MBAR2[0xAC]))
#define MCF5249_SIM_GPIO1_READ (*(vuint32 *)(void *)(&__MBAR2[0xB0]))
#define MCF5249_SIM_GPIO1_OUT (*(vuint32 *)(void *)(&__MBAR2[0xB4]))
#define MCF5249_SIM_GPIO1_ENABLE (*(vuint32 *)(void *)(&__MBAR2[0xB8]))
#define MCF5249_SIM_GPIO1_FUNC (*(vuint32 *)(void *)(&__MBAR2[0xBC]))
#define MCF5249_SIM_GPIO_INT_STAT (*(vuint32 *)(void *)(&__MBAR2[0xC0]))
#define MCF5249_SIM_GPIO_INT_CLEAR (*(vuint32 *)(void *)(&__MBAR2[0xC0]))
#define MCF5249_SIM_GPIO_INT_EN (*(vuint32 *)(void *)(&__MBAR2[0xC4]))
#define MCF5249_SIM_INTERRUPT_STAT3 (*(vuint32 *)(void *)(&__MBAR2[0xE0]))
#define MCF5249_SIM_INTERRUPT_CLR3 (*(vuint32 *)(void *)(&__MBAR2[0xE0]))
#define MCF5249_SIM_INTERRUPT_EN3 (*(vuint32 *)(void *)(&__MBAR2[0xE4]))
#define MCF5249_SIM_INTLEV1 (*(vuint32 *)(void *)(&__MBAR2[0x140]))
#define MCF5249_SIM_INTLEV2 (*(vuint32 *)(void *)(&__MBAR2[0x144]))
#define MCF5249_SIM_INTLEV3 (*(vuint32 *)(void *)(&__MBAR2[0x148]))
#define MCF5249_SIM_INTLEV4 (*(vuint32 *)(void *)(&__MBAR2[0x14C]))
#define MCF5249_SIM_INTLEV5 (*(vuint32 *)(void *)(&__MBAR2[0x150]))
#define MCF5249_SIM_INTLEV6 (*(vuint32 *)(void *)(&__MBAR2[0x154]))
#define MCF5249_SIM_INTLEV7 (*(vuint32 *)(void *)(&__MBAR2[0x158]))
#define MCF5249_SIM_INTLEV8 (*(vuint32 *)(void *)(&__MBAR2[0x15C]))
#define MCF5249_SIM_SPURVEC (*(vuint8 *)(void *)(&__MBAR2[0x167]))
#define MCF5249_SIM_INTBASE (*(vuint8 *)(void *)(&__MBAR2[0x16B]))
/* Bit level definitions and macros */
#define MCF5249_SIM_RSR_HRST (0x80)
#define MCF5249_SIM_RSR_SWTR (0x20)
#define MCF5249_SIM_SYPCR_SWE (0x80)
#define MCF5249_SIM_SYPCR_SWRI (0x40)
#define MCF5249_SIM_SYPCR_SWT_2_9 (0x00)
#define MCF5249_SIM_SYPCR_SWT_2_11 (0x08)
#define MCF5249_SIM_SYPCR_SWT_2_13 (0x10)
#define MCF5249_SIM_SYPCR_SWT_2_15 (0x18)
#define MCF5249_SIM_SYPCR_SWT_2_18 (0x20)
#define MCF5249_SIM_SYPCR_SWT_2_20 (0x28)
#define MCF5249_SIM_SYPCR_SWT_2_22 (0x30)
#define MCF5249_SIM_SYPCR_SWT_2_24 (0x38)
#define MCF5249_SIM_SYPCR_SWTA (0x04)
#define MCF5249_SIM_SYPCR_SWTAVAL (0x02)
#define MCF5249_SIM_SWSR_55 (0x55)
#define MCF5249_SIM_SWSR_AA (0xaa)
#define MCF5249_MBAR_BA(a) ((a)&0xFFFFF000)
#define MCF5249_MBAR_WP (0x00000100)
#define MCF5249_MBAR_AM (0x00000040)
#define MCF5249_MBAR_CI (0x00000020)
#define MCF5249_MBAR_SC (0x00000010)
#define MCF5249_MBAR_SD (0x00000008)
#define MCF5249_MBAR_UC (0x00000004)
#define MCF5249_MBAR_UD (0x00000002)
#define MCF5249_MBAR_V (0x00000001)
#define MCF5249_MBAR2_BA(a) ((a)&0xC0000000)
#define MCF5249_MBAR2_LS7 (0x00000080)
#define MCF5249_MBAR2_LS6 (0x00000040)
#define MCF5249_MBAR2_LS5 (0x00000020)
#define MCF5249_MBAR2_LS4 (0x00000010)
#define MCF5249_MBAR2_LS3 (0x00000008)
#define MCF5249_MBAR2_LS2 (0x00000004)
#define MCF5249_MBAR2_LS1 (0x00000002)
#define MCF5249_MBAR2_V (0x00000001)
#define MCF5249_SIM_ICR_AVEC (0x80)
#define MCF5249_SIM_ICR_IL(a) (((a)&0x07)<<2)
#define MCF5249_SIM_ICR_IP_00 (0x00)
#define MCF5249_SIM_ICR_IP_01 (0x01)
#define MCF5249_SIM_ICR_IP_10 (0x02)
#define MCF5249_SIM_ICR_IP_11 (0x03)
#define MCF5249_SIM_IPR_DMA3 (0x00020000)
#define MCF5249_SIM_IPR_DMA2 (0x00010000)
#define MCF5249_SIM_IPR_DMA1 (0x00008000)
#define MCF5249_SIM_IPR_DMA0 (0x00004000)
#define MCF5249_SIM_IPR_UART1 (0x00002000)
#define MCF5249_SIM_IPR_UART0 (0x00001000)
#define MCF5249_SIM_IPR_I2C (0x00000800)
#define MCF5249_SIM_IPR_TIMER1 (0x00000400)
#define MCF5249_SIM_IPR_TIMER0 (0x00000200)
#define MCF5249_SIM_IPR_SWT (0x00000100)
#define MCF5249_SIM_IPR_EINT7 (0x00000080)
#define MCF5249_SIM_IPR_EINT6 (0x00000040)
#define MCF5249_SIM_IPR_EINT5 (0x00000020)
#define MCF5249_SIM_IPR_EINT4 (0x00000010)
#define MCF5249_SIM_IPR_EINT3 (0x00000008)
#define MCF5249_SIM_IPR_EINT2 (0x00000004)
#define MCF5249_SIM_IPR_EINT1 (0x00000002)
#define MCF5249_SIM_IMR_DMA3 (0x00020000)
#define MCF5249_SIM_IMR_DMA2 (0x00010000)
#define MCF5249_SIM_IMR_DMA1 (0x00008000)
#define MCF5249_SIM_IMR_DMA0 (0x00004000)
#define MCF5249_SIM_IMR_UART1 (0x00002000)
#define MCF5249_SIM_IMR_UART0 (0x00001000)
#define MCF5249_SIM_IMR_I2C (0x00000800)
#define MCF5249_SIM_IMR_TIMER1 (0x00000400)
#define MCF5249_SIM_IMR_TIMER0 (0x00000200)
#define MCF5249_SIM_IMR_SWT (0x00000100)
#define MCF5249_SIM_IMR_EINT7 (0x00000080)
#define MCF5249_SIM_IMR_EINT6 (0x00000040)
#define MCF5249_SIM_IMR_EINT5 (0x00000020)
#define MCF5249_SIM_IMR_EINT4 (0x00000010)
#define MCF5249_SIM_IMR_EINT3 (0x00000008)
#define MCF5249_SIM_IMR_EINT2 (0x00000004)
#define MCF5249_SIM_IMR_EINT1 (0x00000002)
#define MCF5249_SIM_AVCR_AVEC7 (0x80)
#define MCF5249_SIM_AVCR_AVEC6 (0x40)
#define MCF5249_SIM_AVCR_AVEC5 (0x20)
#define MCF5249_SIM_AVCR_AVEC4 (0x10)
#define MCF5249_SIM_AVCR_AVEC3 (0x08)
#define MCF5249_SIM_AVCR_AVEC2 (0x04)
#define MCF5249_SIM_AVCR_AVEC1 (0x02)
#define MCF5249_SIM_AVCR_BLK (0x01)
#define MCF5249_SIM_DEVID_PART(a) ((a & 0xFFFFFF00) >> 8)
#define MCF5249_SIM_DEVID_MASK(a) (a & 0x000000FF)
/**********************************************************************
*
* Phase-Locked Loop and Clock Dividers
*
***********************************************************************/
/* Offsets of the registers from the MBAR */
#define MCF5249_PLL_PLLCR (*(vuint32 *)(void *)(&__MBAR2[0x180]))
/* Bit level definitions and macros */
#define MCF5249_PLL_PLLCR_LOCK (0x80000000)
/**********************************************************************
*
* Chip Select Registers
*
***********************************************************************/
/* Offsets of the registers from the MBAR */
#define MCF5249_CS_CSAR0 (*(vuint16 *)(void *)(&__MBAR[0x080]))
#define MCF5249_CS_CSMR0 (*(vuint32 *)(void *)(&__MBAR[0x084]))
#define MCF5249_CS_CSCR0 (*(vuint16 *)(void *)(&__MBAR[0x08A]))
#define MCF5249_CS_CSAR1 (*(vuint16 *)(void *)(&__MBAR[0x08C]))
#define MCF5249_CS_CSMR1 (*(vuint32 *)(void *)(&__MBAR[0x090]))
#define MCF5249_CS_CSCR1 (*(vuint16 *)(void *)(&__MBAR[0x096]))
#define MCF5249_CS_CSAR2 (*(vuint16 *)(void *)(&__MBAR[0x098]))
#define MCF5249_CS_CSMR2 (*(vuint32 *)(void *)(&__MBAR[0x09C]))
#define MCF5249_CS_CSCR2 (*(vuint16 *)(void *)(&__MBAR[0x0A2]))
#define MCF5249_CS_CSAR3 (*(vuint16 *)(void *)(&__MBAR[0x0A4]))
#define MCF5249_CS_CSMR3 (*(vuint32 *)(void *)(&__MBAR[0x0A8]))
#define MCF5249_CS_CSCR3 (*(vuint16 *)(void *)(&__MBAR[0x0AE]))
#define MCF5249_CS_IDECONFIG1 (*(vuint32 *)(void *)(&__MBAR2[0x18C]))
#define MCF5249_CS_IDECONFIG2 (*(vuint32 *)(void *)(&__MBAR2[0x190]))
/* Bit level definitions and macros */
#define MCF5249_CS_CSAR_BA(a) (uint16)(((a)&0xFFFF0000)>>16)
#define MCF5249_CS_CSMR_BAM_4G (0xFFFF0000)
#define MCF5249_CS_CSMR_BAM_2G (0x7FFF0000)
#define MCF5249_CS_CSMR_BAM_1G (0x3FFF0000)
#define MCF5249_CS_CSMR_BAM_512M (0x1FFF0000)
#define MCF5249_CS_CSMR_BAM_256M (0x0FFF0000)
#define MCF5249_CS_CSMR_BAM_128M (0x07FF0000)
#define MCF5249_CS_CSMR_BAM_64M (0x03FF0000)
#define MCF5249_CS_CSMR_BAM_32M (0x01FF0000)
#define MCF5249_CS_CSMR_BAM_16M (0x00FF0000)
#define MCF5249_CS_CSMR_BAM_8M (0x007F0000)
#define MCF5249_CS_CSMR_BAM_4M (0x003F0000)
#define MCF5249_CS_CSMR_BAM_2M (0x001F0000)
#define MCF5249_CS_CSMR_BAM_1M (0x000F0000)
#define MCF5249_CS_CSMR_BAM_512K (0x00070000)
#define MCF5249_CS_CSMR_BAM_256K (0x00030000)
#define MCF5249_CS_CSMR_BAM_128K (0x00010000)
#define MCF5249_CS_CSMR_BAM_64K (0x00000000)
#define MCF5249_CS_CSMR_WP (0x00000100)
#define MCF5249_CS_CSMR_AM (0x00000040)
#define MCF5249_CS_CSMR_CI (0x00000020)
#define MCF5249_CS_CSMR_SC (0x00000010)
#define MCF5249_CS_CSMR_SD (0x00000008)
#define MCF5249_CS_CSMR_UC (0x00000004)
#define MCF5249_CS_CSMR_UD (0x00000002)
#define MCF5249_CS_CSMR_V (0x00000001)
#define MCF5249_CS_CSCR_WS(a) ((a & 0xF)<<10)
#define MCF5249_CS_CSCR_AA (0x0100)
#define MCF5249_CS_CSCR_PS (0x00C0)
#define MCF5249_CS_CSCR_BSTR (0x0010)
#define MCF5249_CS_CSCR_BSTW (0x0008)
/**********************************************************************
*
* Ports Registers Description
*
***********************************************************************/
/**********************************************************************
*
* QSPI Module Registers Description
*
***********************************************************************/
#define MCF5249_QSPI_QMR (*(vuint32 *)(void *)(&__MBAR[0x400]))
#define MCF5249_QSPI_QDLYR (*(vuint32 *)(void *)(&__MBAR[0x404]))
#define MCF5249_QSPI_QWR (*(vuint32 *)(void *)(&__MBAR[0x408]))
#define MCF5249_QSPI_QIR (*(vuint32 *)(void *)(&__MBAR[0x40C]))
#define MCF5249_QSPI_QAR (*(vuint32 *)(void *)(&__MBAR[0x410]))
#define MCF5249_QSPI_QDR (*(vuint32 *)(void *)(&__MBAR[0x414]))
/**********************************************************************
*
* DMA Module Registers Description
*
***********************************************************************/
#define MCF5249_DMA_ROUTE (*(vuint8 *)(void *)(&__MBAR2[0x188]))
#define MCF5249_DMA0_SAR (*(vuint32 *)(void *)(&__MBAR[0x300]))
#define MCF5249_DMA0_DAR (*(vuint32 *)(void *)(&__MBAR[0x304]))
#define MCF5249_DMA0_DCR (*(vuint16 *)(void *)(&__MBAR[0x308]))
#define MCF5249_DMA0_BCR (*(vuint16 *)(void *)(&__MBAR[0x30C]))
#define MCF5249_DMA0_DSR (*(vuint8 *)(void *)(&__MBAR[0x310]))
#define MCF5249_DMA0_DIVR (*(vuint8 *)(void *)(&__MBAR[0x314]))
#define MCF5249_DMA1_SAR (*(vuint32 *)(void *)(&__MBAR[0x340]))
#define MCF5249_DMA1_DAR (*(vuint32 *)(void *)(&__MBAR[0x344]))
#define MCF5249_DMA1_DCR (*(vuint16 *)(void *)(&__MBAR[0x348]))
#define MCF5249_DMA1_BCR (*(vuint16 *)(void *)(&__MBAR[0x34C]))
#define MCF5249_DMA1_DSR (*(vuint8 *)(void *)(&__MBAR[0x350]))
#define MCF5249_DMA1_DIVR (*(vuint8 *)(void *)(&__MBAR[0x354]))
#define MCF5249_DMA2_SAR (*(vuint32 *)(void *)(&__MBAR[0x380]))
#define MCF5249_DMA2_DAR (*(vuint32 *)(void *)(&__MBAR[0x384]))
#define MCF5249_DMA2_DCR (*(vuint16 *)(void *)(&__MBAR[0x388]))
#define MCF5249_DMA2_BCR (*(vuint16 *)(void *)(&__MBAR[0x38C]))
#define MCF5249_DMA2_DSR (*(vuint8 *)(void *)(&__MBAR[0x390]))
#define MCF5249_DMA2_DIVR (*(vuint8 *)(void *)(&__MBAR[0x394]))
#define MCF5249_DMA3_SAR (*(vuint32 *)(void *)(&__MBAR[0x3C0]))
#define MCF5249_DMA3_DAR (*(vuint32 *)(void *)(&__MBAR[0x3C4]))
#define MCF5249_DMA3_DCR (*(vuint16 *)(void *)(&__MBAR[0x3C8]))
#define MCF5249_DMA3_BCR (*(vuint16 *)(void *)(&__MBAR[0x3CC]))
#define MCF5249_DMA3_DSR (*(vuint8 *)(void *)(&__MBAR[0x3D0]))
#define MCF5249_DMA3_DIVR (*(vuint8 *)(void *)(&__MBAR[0x3D4]))
/**********************************************************************
*
* Mbus (IIC) Module Registers Description
*
***********************************************************************/
#define MCF5249_I2C_MADR (*(vuint8 *)(void *)(&__MBAR[0x280]))
#define MCF5249_I2C_MFDR (*(vuint8 *)(void *)(&__MBAR[0x284]))
#define MCF5249_I2C_MBCR (*(vuint8 *)(void *)(&__MBAR[0x288]))
#define MCF5249_I2C_MBSR (*(vuint8 *)(void *)(&__MBAR[0x28C]))
#define MCF5249_I2C_MBDR (*(vuint8 *)(void *)(&__MBAR[0x290]))
#define MCF5249_I2C2_MADR (*(vuint8 *)(void *)(&__MBAR2[0x440]))
#define MCF5249_I2C2_MFDR (*(vuint8 *)(void *)(&__MBAR2[0x444]))
#define MCF5249_I2C2_MBCR (*(vuint8 *)(void *)(&__MBAR2[0x448]))
#define MCF5249_I2C2_MBSR (*(vuint8 *)(void *)(&__MBAR2[0x44C]))
#define MCF5249_I2C2_MBDR (*(vuint8 *)(void *)(&__MBAR2[0x450]))
/**********************************************************************
*
* USART Module Registers Description
*
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