📄 mcf5407.h
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#define MCF5407_DRAMC_DCMR_MASK_32M (0x01FC0000) /* DRAM Size of 32M */
#define MCF5407_DRAMC_DCMR_MASK_16M (0x00FC0000) /* DRAM Size of 16M */
#define MCF5407_DRAMC_DCMR_MASK_8M (0x007C0000) /* DRAM Size of 8M */
#define MCF5407_DRAMC_DCMR_MASK_4M (0x003C0000) /* DRAM Size of 4M */
#define MCF5407_DRAMC_DCMR_MASK_2M (0x001C0000) /* DRAM Size of 2M */
#define MCF5407_DRAMC_DCMR_MASK_1M (0x000C0000) /* DRAM Size of 1M */
#define MCF5407_DRAMC_DCMR_MASK_1024K (0x00040000) /* DRAM Size of 1024K */
#define MCF5407_DRAMC_DCMR_MASK_512K (0x00000000) /* DRAM Size of 512K */
#define MCF5407_DRAMC_DCMR_WP (0x00000100) /* Write Protect */
#define MCF5407_DRAMC_DCMR_CPU (0x00000040) /* CPU Space Ignored */
#define MCF5407_DRAMC_DCMR_AM (0x00000020) /* Alternate Master Ignored */
#define MCF5407_DRAMC_DCMR_SC (0x00000010) /* Supervisor Code Ignored */
#define MCF5407_DRAMC_DCMR_SD (0x00000008) /* Supervisor Data Ignored */
#define MCF5407_DRAMC_DCMR_UC (0x00000004) /* User Code Ignored */
#define MCF5407_DRAMC_DCMR_UD (0x00000002) /* User Data Ignored */
#define MCF5407_DRAMC_DCMR_V (0x00000001) /* Valid Register */
/* Controls used only by Asynchronous DRAM*/
#define MCF5407_DRAMC_DCR_RRA_2 (0x0000) /* Refresh RAS Asserted 2 Clocks */
#define MCF5407_DRAMC_DCR_RRA_3 (0x0800) /* Refresh RAS Asserted 3 Clocks */
#define MCF5407_DRAMC_DCR_RRA_4 (0x1000) /* Refresh RAS Asserted 4 Clocks */
#define MCF5407_DRAMC_DCR_RRA_5 (0x1800) /* Refresh RAS Asserted 5 Clocks */
#define MCF5407_DRAMC_DCR_RRP_1 (0x0000) /* Refresh RAS Precharged 3 Clks */
#define MCF5407_DRAMC_DCR_RRP_2 (0x0200) /* Refresh RAS Precharged 3 Clks */
#define MCF5407_DRAMC_DCR_RRP_3 (0x0400) /* Refresh RAS Precharged 3 Clks */
#define MCF5407_DRAMC_DCR_RRP_4 (0x0600) /* Refresh RAS Precharged 3 Clks */
#define MCF5407_DRAMC_DACR_CAS_1 (0x00000000) /* CAS Active 1 Clock */
#define MCF5407_DRAMC_DACR_CAS_2 (0x00001000) /* CAS Active 2 Clocks */
#define MCF5407_DRAMC_DACR_CAS_3 (0x00002000) /* CAS Active 3 Clocks */
#define MCF5407_DRAMC_DACR_CAS_4 (0x00003000) /* CAS Active 4 Clocks */
#define MCF5407_DRAMC_DACR_RP_1 (0x00000000) /* RAS Precharge 1 Clock */
#define MCF5407_DRAMC_DACR_RP_2 (0x00000400) /* RAS Precharge 2 Clocks */
#define MCF5407_DRAMC_DACR_RP_3 (0x00000800) /* RAS Precharge 3 Clocks */
#define MCF5407_DRAMC_DACR_RP_4 (0x00000C00) /* RAS Precharge 4 Clocks */
#define MCF5407_DRAMC_DACR_RNCN (0x00000200) /* RAS Negate to CAS Negate */
#define MCF5407_DRAMC_DACR_RCD_1 (0x00000000) /* 1 Clock Between RAS and CAS */
#define MCF5407_DRAMC_DACR_RCD_2 (0x00000100) /* 2 Clocks Between RAS and CAS */
#define MCF5407_DRAMC_DACR_EDO (0x00000040) /* Extended Data Out */
#define MCF5407_DRAMC_DACR_PM_OFF (0x00000000) /* No Page Mode */
#define MCF5407_DRAMC_DACR_PM_BURST (0x00000004) /* Page Mode on Burst Only */
#define MCF5407_DRAMC_DACR_PM_ON (0x0000000C) /* Continuous Page Mode */
/* Controls used only by Synchronous DRAM */
#define MCF5407_DRAMC_DCR_COC (0x1000) /* Command on Clock Enable */
#define MCF5407_DRAMC_DCR_IS (0x0800) /* Initiate Self Refresh Command */
#define MCF5407_DRAMC_DCR_RTIM_3 (0x0000) /* 3 Clocks Between REF and ACTV Cmds */
#define MCF5407_DRAMC_DCR_RTIM_6 (0x0200) /* 6 Clocks Between REF and ACTV Cmds */
#define MCF5407_DRAMC_DCR_RTIM_9 (0x0400) /* 9 Clocks Between REF and ACTV Cmds */
#define MCF5407_DRAMC_DACR_CASL_1 (0x00000000) /* 1 Clock From CAS to Data */
#define MCF5407_DRAMC_DACR_CASL_2 (0x00001000) /* 2 Clock From CAS to Data */
#define MCF5407_DRAMC_DACR_CASL_3 (0x00002000) /* 3 Clock From CAS to Data */
#define MCF5407_DRAMC_DACR_CBM(a) (((a)&0x00000007)<<8) /* Command and Bank Mux */
#define MCF5407_DRAMC_DACR_IMRS (0x00000040) /* Initiate Mode Register Set Cmd */
#define MCF5407_DRAMC_DACR_IP (0x00000008) /* Initiate Precharge All Command */
#define MCF5407_DRAMC_DACR_PM (0x00000004) /* Continuous Page Mode */
/**********************************************************************/
/* UART Module, UART */
/**********************************************************************/
#define MCF5407_UART0_UMR (0x01C0)
#define MCF5407_UART0_USR (0x01C4)
#define MCF5407_UART0_UCSR (0x01C4)
#define MCF5407_UART0_UCR (0x01C8)
#define MCF5407_UART0_URB (0x01CC)
#define MCF5407_UART0_UTB (0x01CC)
#define MCF5407_UART0_UIPCR (0x01D0)
#define MCF5407_UART0_UACR (0x01D0)
#define MCF5407_UART0_UISR (0x01D4)
#define MCF5407_UART0_UIMR (0x01D4)
#define MCF5407_UART0_UBG1 (0x01D8)
#define MCF5407_UART0_UBG2 (0x01DC)
#define MCF5407_UART0_UIVR (0x01F0)
#define MCF5407_UART0_UIP (0x01F4)
#define MCF5407_UART0_UOP1 (0x01F8)
#define MCF5407_UART0_UOP0 (0x01FC)
#define MCF5407_UART1_UMR (0x0200)
#define MCF5407_UART1_RXLVL (0x0201)
#define MCF5407_UART1_MODCTL (0x0202)
#define MCF5407_UART1_TXLVL (0x0203)
#define MCF5407_UART1_USR (0x0204)
#define MCF5407_UART1_UCSR (0x0204)
#define MCF5407_UART1_RSMP (0x0206)
#define MCF5407_UART1_TSPC (0x0207)
#define MCF5407_UART1_UCR (0x0208)
#define MCF5407_UART1_URB (0x020C)
#define MCF5407_UART1_UTB (0x020C)
#define MCF5407_UART1_UIPCR (0x0210)
#define MCF5407_UART1_UACR (0x0210)
#define MCF5407_UART1_UISR (0x0214)
#define MCF5407_UART1_UIMR (0x0214)
#define MCF5407_UART1_UBG1 (0x0218)
#define MCF5407_UART1_UBG2 (0x021C)
#define MCF5407_UART1_UIVR (0x0230)
#define MCF5407_UART1_UIP (0x0234)
#define MCF5407_UART1_UOP1 (0x0238)
#define MCF5407_UART1_UOP0 (0x023C)
/* Read access macros for general use */
#define MCF5407_RD_UART0_UMR(IMMP) Mcf5407_iord(IMMP,MCF5407_UART0_UMR,8)
#define MCF5407_RD_UART0_USR(IMMP) Mcf5407_iord(IMMP,MCF5407_UART0_USR,8)
#define MCF5407_RD_UART0_URB(IMMP) Mcf5407_iord(IMMP,MCF5407_UART0_URB,8)
#define MCF5407_RD_UART0_UIPCR(IMMP) Mcf5407_iord(IMMP,MCF5407_UART0_UIPCR,8)
#define MCF5407_RD_UART0_UISR(IMMP) Mcf5407_iord(IMMP,MCF5407_UART0_UISR,8)
#define MCF5407_RD_UART0_UBG1(IMMP) Mcf5407_iord(IMMP,MCF5407_UART0_UBG1,8)
#define MCF5407_RD_UART0_UBG2(IMMP) Mcf5407_iord(IMMP,MCF5407_UART0_UBG2,8)
#define MCF5407_RD_UART0_UIVR(IMMP) Mcf5407_iord(IMMP,MCF5407_UART0_UIVR,8)
#define MCF5407_RD_UART0_UIP(IMMP) Mcf5407_iord(IMMP,MCF5407_UART0_UIP,8)
#define MCF5407_RD_UART1_UMR(IMMP) Mcf5407_iord(IMMP,MCF5407_UART1_UMR,8)
#define MCF5407_RD_UART1_RXLVL(IMMP) Mcf5407_iord(IMMP,MCF5407_UART1_RXLVL,8)
#define MCF5407_RD_UART1_MODCTL(IMMP) Mcf5407_iord(IMMP,MCF5407_UART1_MODCTL,8)
#define MCF5407_RD_UART1_TXLVL(IMMP) Mcf5407_iord(IMMP,MCF5407_UART1_TXLVL,8)
#define MCF5407_RD_UART1_USR(IMMP) Mcf5407_iord(IMMP,MCF5407_UART1_USR,8)
#define MCF5407_RD_UART1_RSMP(IMMP) Mcf5407_iord(IMMP,MCF5407_UART1_RSMP,8)
#define MCF5407_RD_UART1_TSPC(IMMP) Mcf5407_iord(IMMP,MCF5407_UART1_TSPC,8)
#define MCF5407_RD_UART1_URB(IMMP) Mcf5407_iord(IMMP,MCF5407_UART1_URB,8)
#define MCF5407_RD_UART1_UIPCR(IMMP) Mcf5407_iord(IMMP,MCF5407_UART1_UIPCR,8)
#define MCF5407_RD_UART1_UISR(IMMP) Mcf5407_iord(IMMP,MCF5407_UART1_UISR,8)
#define MCF5407_RD_UART1_UBG1(IMMP) Mcf5407_iord(IMMP,MCF5407_UART1_UBG1,8)
#define MCF5407_RD_UART1_UBG2(IMMP) Mcf5407_iord(IMMP,MCF5407_UART1_UBG2,8)
#define MCF5407_RD_UART1_UIVR(IMMP) Mcf5407_iord(IMMP,MCF5407_UART1_UIVR,8)
#define MCF5407_RD_UART1_UIP(IMMP) Mcf5407_iord(IMMP,MCF5407_UART1_UIP,8)
/* Write access macros for general use */
#define MCF5407_WR_UART0_UMR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_UART0_UMR,8,DATA)
#define MCF5407_WR_UART0_UCSR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_UART0_UCSR,8,DATA)
#define MCF5407_WR_UART0_UCR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_UART0_UCR,8,DATA)
#define MCF5407_WR_UART0_UTB(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_UART0_UTB,8,DATA)
#define MCF5407_WR_UART0_UACR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_UART0_UACR,8,DATA)
#define MCF5407_WR_UART0_UIMR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_UART0_UIMR,8,DATA)
#define MCF5407_WR_UART0_UBG1(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_UART0_UBG1,8,DATA)
#define MCF5407_WR_UART0_UBG2(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_UART0_UBG2,8,DATA)
#define MCF5407_WR_UART0_UIVR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_UART0_UIVR,8,DATA)
#define MCF5407_WR_UART0_UOP1(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_UART0_UOP1,8,DATA)
#define MCF5407_WR_UART0_UOP0(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_UART0_UOP0,8,DATA)
#define MCF5407_WR_UART1_UMR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_UART1_UMR,8,DATA)
#define MCF5407_WR_UART1_RXLVL(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_UART1_RXLVL,8,DATA)
#define MCF5407_WR_UART1_MODCTL(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_UART1_MODCTL,8,DATA)
#define MCF5407_WR_UART1_TXLVL(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_UART1_TXLVL,8,DATA)
#define MCF5407_WR_UART1_UCSR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_UART1_UCSR,8,DATA)
#define MCF5407_WR_UART1_UCR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_UART1_UCR,8,DATA)
#define MCF5407_WR_UART1_UTB(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_UART1_UTB,8,DATA)
#define MCF5407_WR_UART1_UACR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_UART1_UACR,8,DATA)
#define MCF5407_WR_UART1_UIMR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_UART1_UIMR,8,DATA)
#define MCF5407_WR_UART1_UBG1(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_UART1_UBG1,8,DATA)
#define MCF5407_WR_UART1_UBG2(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_UART1_UBG2,8,DATA)
#define MCF5407_WR_UART1_UIVR(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_UART1_UIVR,8,DATA)
#define MCF5407_WR_UART1_UOP1(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_UART1_UOP1,8,DATA)
#define MCF5407_WR_UART1_UOP0(IMMP,DATA) \
Mcf5407_iowr(IMMP,MCF5407_UART1_UOP0,8,DATA)
#define MCF5407_UART_UMR1_RXRTS (0x80)
#define MCF5407_UART_UMR1_RXIRQ (0x40)
#define MCF5407_UART_UMR1_ERR (0x20)
#define MCF5407_UART_UMR1_PM1 (0x10)
#define MCF5407_UART_UMR1_PM0 (0x08)
#define MCF5407_UART_UMR1_PMT (0x04)
#define MCF5407_UART_UMR1_BC1 (0x02)
#define MCF5407_UART_UMR1_BC0 (0x01)
#define MCF5407_UART_UMR1_PM_MULTI_ADDR (0x1C)
#define MCF5407_UART_UMR1_PM_MULTI_DATA (0x18)
#define MCF5407_UART_UMR1_PM_NONE (0x10)
#define MCF5407_UART_UMR1_PM_FORCE_HI (0x0C)
#define MCF5407_UART_UMR1_PM_FORCE_LO (0x08)
#define MCF5407_UART_UMR1_PM_ODD (0x04)
#define MCF5407_UART_UMR1_PM_EVEN (0x00)
#define MCF5407_UART_UMR1_BC_5 (0x00)
#define MCF5407_UART_UMR1_BC_6 (0x01)
#define MCF5407_UART_UMR1_BC_7 (0x02)
#define MCF5407_UART_UMR1_BC_8 (0x03)
#define MCF5407_UART_UMR2_CM1 (0x80)
#define MCF5407_UART_UMR2_CM0 (0x40)
#define MCF5407_UART_UMR2_TXRTS (0x20)
#define MCF5407_UART_UMR2_TXCTS (0x10)
#define MCF5407_UART_UMR2_SB3 (0x08)
#define MCF5407_UART_UMR2_SB2 (0x04)
#define MCF5407_UART_UMR2_SB1 (0x02)
#define MCF5407_UART_UMR2_SB0 (0x01)
#define MCF5407_UART_UMR2_CM_NORMAL (0x00)
#define MCF5407_UART_UMR2_CM_ECHO (0x40)
#define MCF5407_UART_UMR2_CM_LOCAL_LOOP (0x80)
#define MCF5407_UART_UMR2_CM_REMOTE_LOOP (0xC0)
#define MCF5407_UART_UMR2_STOP_BITS_1 (0x07)
#define MCF5407_UART_UMR2_STOP_BITS_15 (0x08)
#define MCF5407_UART_UMR2_STOP_BITS_2 (0x0F)
#define MCF5407_UART_MODCTL_ACRB (0x80)
#define MCF5407_UART_MODCTL_AWR (0x40)
#define MCF5407_UART_MODCTL_DSL_00 (0x00)
#define MCF5407_UART_MODCTL_DSL_01 (0x10)
#define MCF5407_UART_MODCTL_DSL_10 (0x20)
#define MCF5407_UART_MODCTL_DSL_11 (0x30)
#define MCF5407_UART_MODCTL_DTS1 (0x08)
#define MCF5407_UART_MODCTL_SHDIR (0x04)
#define MCF5407_UART_MODCTL_MODE_00 (0x00)
#define MCF5407_UART_MODCTL_MODE_01 (0x01)
#define MCF5407_UART_MODCTL_MODE_10 (0x02)
#define MCF5407_UART_MODCTL_MODE_11 (0x03)
#define MCF5407_UART_USR_RB (0x80)
#define MCF5407_UART_USR_FE (0x40)
#define MCF5407_UART_USR_PE (0x20)
#define MCF5407_UART_USR_OE (0x10)
#define MCF5407_UART_USR_TXEMP (0x08)
#define MCF5407_UART_USR_TXRDY (0x04)
#define MCF5407_UART_USR_FFULL (0x02)
#define MCF5407_UART_USR_RXRDY (0x01)
#define MCF5407_UART_UCSR_RCS3 (0x80)
#define MCF5407_UART_UCSR_RCS2 (0x40)
#define MCF5407_UART_UCSR_RCS1 (0x20)
#define MCF5407_UART_UCSR_RCS0 (0x10)
#define MCF5407_UART_UCSR_TCS3 (0x08)
#define MCF5407_UART_UCSR_TCS2 (0x04)
#define MCF5407_UART_UCSR_TCS1 (0x02)
#define MCF5407_UART_UCSR_TCS0 (0x01)
#define MCF5407_UART_UCSR_RX_TIMER (0xD0)
#define MCF5407_UART_UCSR_RX_16EXT (0xE0)
#define MCF5407_UART_UCSR_RX_1EXT (0xF0)
#define MCF5407_UART_UCSR_TX_TIMER (0x0D)
#define MCF5407_UART_UCSR_TX_16EXT (0x0E)
#define MCF5407_UART_UCSR_TX_1EXT (0x0F)
#define MCF5407_UART_UCR_MISC2 (0x40)
#define MCF5407_UART_UCR_MISC1 (0x20)
#define MCF5407_UART_UCR_MISC0 (0x10)
#define MCF5407_UART_UCR_TC1 (0x08)
#define MCF5407_UART_UCR_TC0 (0x04)
#define MCF5407_UART_UCR_RC1 (0x02)
#define MCF5407_UART_UCR_RC0 (0x01)
#define MCF5407_UART_UCR_NONE (0x00)
#define MCF5407_UART_UCR_STOP_BREAK (0x70)
#define MCF5407_UART_UCR_START_BREAK (0x60)
#define MCF5407_UART_UCR_RESET_BKCHGINT (0x50)
#define MCF5407_UART_UCR_RESET_ERROR (0x40)
#define MCF5407_UART_UCR_RESET_TX (0x30)
#define MCF5407_UART_UCR_RESET_RX (0x20)
#define MCF5407_UART_UCR_RESET_MR (0x10)
#define MCF5407_UART_UCR_TX_DISABLED (0x08)
#define MCF5407_UART_UCR_TX_ENABLED (0x04)
#define MCF5407_UART_UCR_RX_DISABLED (0x02)
#define MCF5407_UART_UCR_RX_ENABLED (0x01)
#define MCF5407_UART_UIPCR_COS (0x10)
#define MCF5407_UART_UIPCR_CTS (0x01)
#define MCF5407_UART_UACR_IEC (0x01)
#define MCF5407_UART_UISR_COS (0x80)
#define MCF5407_UART_UISR_DB (0x04)
#define MCF5407_UART_UISR_RXRDY (0x02)
#define MCF5407_UART_UISR_TXRDY (0x01)
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