m5282evb.cfg

Coldfire MCF5282 DBug bootloader

Reset
Delay 200
Delay 200
Stop

; Set VBR to the beginning of what will be SDRAM
; VBR is an absolute CPU register
; SDRAM is at 0x00000000+0x0400000

;writecontrolreg 0x0801 0x00000000

; Set IPSBAR = 0x40000001
; IPSBAR is an absolute CPU register
; NOTE:  All subsequent writes to MBAR relative
;        locations must be changed if MBAR is moved
;writecontrolreg 0x0000 0x40000001

; Set RAMBAR = 0x20000001
; RAMBAR is an absolute CPU register
; This is the location of the internal 64k of SRAM on the chip

writecontrolreg 0x0C05 0x20000001

; Set FLASHBAR = 0xF0000001
; FLASHBAR is an absolute CPU register
; This is the location of the internal 64k of SRAM on the chip

;writecontrolreg 0x0C04 0xF0000001


; Set ACR0 = 0x00000000

;writecontrolreg 0x04 0x00000000

; Set ACR1 = 0x00000000

;writecontrolreg 0x05 0x00000000


; 2MB FLASH on CS0 at 0xFFE00000

writemem.w 0x40000080   0xFFE0		; CSAR0
writemem.l 0x40000084   0x001F0001	; CSMR0
writemem.w 0x4000008A   0x1980		; CSCR0


delay 100

; SDRAM
; Like the 5307 and 5407 Cadre 3 boards, this board uses DCR,DACR, DMR to access SDRAM

;writemem.w 0x40000040   0x023C	 ; DCR
;writemem.l 0x40000048   0x00002300 ; DACR0
;writemem.l 0x4000004C   0x00FC0001 ; DMR0

;writemem.l 0x40000048   0x00002308 ; DACR0

;delay 400

;writemem.l 0x00000000   0xA567A234 ; write data to 0x0000_0000

;delay 400

;writemem.l 0x40000048   0x0000A300 ; DACR0
;writemem.l 0x40000048   0x0000A340 ; DACR0

;delay 2000

;writemem.l 0x00000400   0x00000000 ; Write SDRAM mode register



; Wait a bit

delay 600