📄 hardware.lst
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/////////////////////////////////////////////////////////////////
// Note: This register map to the P_INT_Ctrl(0x7010)
// User's interrupt setting have to combine with this register
// while co-work with SACM library.
//
// See. following function for example:
// F_SP_SACM_A2000_Init_:
// F_SP_SACM_S480_Init_:
// F_SP_SACM_S240_Init_:
// F_SP_SACM_MS01_Init_:
// F_SP_SACM_DVR_Init_:
//////////////////////////////////////////////////
000002F5 .IRAM
.PUBLIC R_InterruptStatus
000002F5 00 00 .VAR R_InterruptStatus = 0 //
//////////////////////////////////////////////////
.DEFINE C_RampDelayTime 32
.DEFINE C_QueueSize 144
000002F6 00 00 .VAR R_Queue
000002F7 00 00 00 00 .DW C_QueueSize-1 DUP(0)
00 00 00 00
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00 00
00000386 00 00 .VAR R_ReadIndex
00000387 00 00 .VAR R_WriteIndex
00008FB8 .CODE
///////////////////////////////////////////
// Function: Initial Queue
// Destory: R1,r2
///////////////////////////////////////////
_SP_InitQueue: .PROC
_SP_InitQueue_A2000:
_SP_InitQueue_S480:
_SP_InitQueue_S240:
_SP_InitQueue_MS01:
_SP_InitQueue_DVR:
F_SP_InitQueue_A2000:
F_SP_InitQueue_S480:
F_SP_InitQueue_S240:
F_SP_InitQueue_MS01:
F_SP_InitQueue_DVR:
F_SP_InitQueue:
00008FB8 09 93 F6 02 r1 = R_Queue
00008FBA 40 94 r2 = 0
L_ClearQueueLoop?:
00008FBB D1 D4 [r1++] = r2
00008FBC 09 43 86 03 cmp r1, R_Queue+C_QueueSize
00008FBE 44 4E jne L_ClearQueueLoop?
00008FBF 40 92 r1 = 0
00008FC0 19 D3 86 03 [R_ReadIndex] = r1
00008FC2 19 D3 87 03 [R_WriteIndex] = r1
00008FC4 90 9A RETF
.ENDP
///////////////////////////////////////////
// Function: Get a data form Queue
// Output: R1: Data
// R2: return value
// Destory: R1,R2
///////////////////////////////////////////
F_SP_ReadQueue_A2000:
F_SP_ReadQueue_S480:
F_SP_ReadQueue_S240:
F_SP_ReadQueue_MS01:
F_SP_ReadQueue_DVR:
F_SP_ReadQueue:
00008FC5 12 95 86 03 r2 = [R_ReadIndex]
00008FC7 12 45 87 03 cmp r2,[R_WriteIndex]
00008FC9 0D 5E je L_RQ_QueueEmpty
00008FCA 0A 05 F6 02 r2 += R_Queue // get queue data address
00008FCC C2 92 r1 = [r2]
00008FCD 12 95 86 03 r2 = [R_ReadIndex]
00008FCF 41 04 r2 += 1
00008FD0 0A 45 90 00 cmp r2, C_QueueSize
00008FD2 01 4E jne L_RQ_NotQueueBottom
00008FD3 40 94 r2 = 0
L_RQ_NotQueueBottom:
00008FD4 1A D5 86 03 [R_ReadIndex] = r2
//r2 = 0x0000 // get queue data
00008FD6 90 9A retf
L_RQ_QueueEmpty:
//r2 = 0x8000 // queue empty
00008FD7 90 9A retf
///////////////////////////////////////////
// Function: Get a data from Queue but do
// not change queue index
// R1: output
// Destory: R1,R2
///////////////////////////////////////////
F_SP_ReadQueue_NIC:
F_SP_ReadQueue_NIC_A2000:
F_SP_ReadQueue_NIC_S480:
F_SP_ReadQueue_NIC_S240:
F_SP_ReadQueue_NIC_MS01:
F_SP_ReadQueue_NIC_DVR:
00008FD8 12 95 86 03 r2 = [R_ReadIndex]
00008FDA 12 45 87 03 cmp r2,[R_WriteIndex]
00008FDC 03 5E je L_RQ_QueueEmpty?
00008FDD 0A 05 F6 02 r2 += R_Queue // get queue data index
00008FDF C2 92 r1 = [r2]
L_RQ_QueueEmpty?:
00008FE0 90 9A RETF
///////////////////////////////////////////
// Function: Put a data to Queue
// R1: Input
// Destory: R1,R2
///////////////////////////////////////////
F_SP_WriteQueue_A2000:
F_SP_WriteQueue_S480:
F_SP_WriteQueue_S240:
F_SP_WriteQueue_MS01:
F_SP_WriteQueue_DVR:
F_SP_WriteQueue:
00008FE1 12 95 87 03 r2 = [R_WriteIndex] // put data to queue
00008FE3 0A 05 F6 02 r2 += R_Queue
00008FE5 C2 D2 [r2] = r1
00008FE6 12 95 87 03 r2 = [R_WriteIndex]
00008FE8 41 04 r2 += 1
00008FE9 0A 45 90 00 cmp r2, C_QueueSize
00008FEB 01 4E jne L_WQ_NotQueueBottom
00008FEC 40 94 r2 = 0
L_WQ_NotQueueBottom:
00008FED 1A D5 87 03 [R_WriteIndex] = r2
00008FEF 90 9A RETF
///////////////////////////////////////////
// Function: Test Queue Status
// o/p: R1
// Destory: R1
///////////////////////////////////////////
F_SP_TestQueue_A2000:
F_SP_TestQueue_S480:
F_SP_TestQueue_S240:
F_SP_TestQueue_MS01:
F_SP_TestQueue_DVR:
F_SP_TestQueue:
//... Test Queue Empty ...
00008FF0 11 93 86 03 r1 = [R_ReadIndex]
00008FF2 11 43 87 03 cmp r1,[R_WriteIndex]
00008FF4 12 5E je L_TQ_QueueEmpty
//... Test Queue Full ...
00008FF5 11 93 86 03 r1 = [R_ReadIndex] // For N Queue Full: 1.R=0 and W=N-1 2. R<>0 and W=R-1
00008FF7 05 4E jnz L_TQ_JudgeCond2
00008FF8 11 93 87 03 r1 = [R_WriteIndex]
00008FFA 09 43 8F 00 cmp r1, C_QueueSize-1 // Cond1
00008FFC 08 5E je L_TQ_QueueFull
L_TQ_JudgeCond2:
00008FFD 11 93 86 03 r1 = [R_ReadIndex]
00008FFF 41 22 r1 -=1
00009000 11 43 87 03 cmp r1,[R_WriteIndex]
00009002 02 5E je L_TQ_QueueFull
00009003 40 92 r1 = 0 // not Full, not empty
00009004 90 9A retf
L_TQ_QueueFull:
00009005 41 92 r1 = 1 // full
00009006 90 9A retf
L_TQ_QueueEmpty:
00009007 42 92 r1 = 2 // empty
00009008 90 9A retf
///////////////////////////////////////////////////////////////////////////////
// Function: The partial code of hardware setting of SACM_A2000_Initial()
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