📄 dss_aisr.lst
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3 .endif
3 .eval regmask >> 1, regmask
3 .eval BITNUM + 1, BITNUM
3 .endloop
4 .if (1008 & 1)
4 .break
4 .endif
4 .eval 1008 >> 1, regmask
4 .eval 0 + 1, BITNUM
4 .if (504 & 1)
4 .break
4 .endif
4 .eval 504 >> 1, regmask
4 .eval 1 + 1, BITNUM
4 .if (252 & 1)
4 .break
4 .endif
4 .eval 252 >> 1, regmask
4 .eval 2 + 1, BITNUM
4 .if (126 & 1)
4 .break
4 .endif
4 .eval 126 >> 1, regmask
4 .eval 3 + 1, BITNUM
4 .if (63 & 1)
4 .break
2 .eval 1008 & ~(1 << 4), bmask
2 .asg b4, TMPB
2 .asg SP, SPB
TMS320C6x COFF Assembler Version 4.00 Fri Feb 16 15:51:02 2001
Copyright (c) 1996-2000 Texas Instruments Incorporated
dss_aisr.s62 PAGE 16
2 .eval 6 - 1, b_bitcount
2
2 .if (1008 = 0) | (992 = 0)
2 .if (a_bitcount > 0)
2 .asg amask, mask
2 .asg A, reg
2 .asg TMPB, tmpreg
2 .elseif (b_bitcount > 0)
2 .asg bmask, mask
2 .asg B, reg
2 .asg TMPA, tmpreg
2 .elseif (cmask > 0)
2 ; both amask and bmask = 0
2 FIRST_BIT_NUM cmask, bitn_c
2 BIT_NUM_2_CREG bitn_c, creg0
2 .endif
2 .endif
2
2 000001d4 013DD4F4 stw a2, *SP--[14] ; CODE
2 000001d8 013C11A0 mv SP, a2 ; CODE
2
2 .if (0 = 0)
2 .if (-1 = -1)
2 ; both amask and bmask non-zero
2
2 000001e0 023DA2F7 stw b4, *+SP[13] ; CODE
2 000001e4 01898274 || stw a3, *+a2[13 - 1] ; CODE
2
2 .else
2 ; both amask and bmask = 0
2
2 stw TMPB, *+SPB[offset] ; CODE
2 || stw TMPA, *+SPA[offset - 1] ; CODE
2 || mvc creg0, TMPB ; CODE
2
2 .endif
2 .else
2 ; one of amask or bmask is 0, but not both
2 FIRST_BIT_NUM mask, bitn_next
2
2 stw TMPB, *+SPB[offset] ; CODE
2 || stw TMPA, *+SPA[offset - 1] ; CODE
2 || mv :reg::bitn_next:, tmpreg ; CODE
2
2 .asg 0, mask
2 .endif
2
2 .eval 13 - 2, offset
2
2 ;
2 ; This loop handles when both A and B registers need saving
2 ;
2 .loop
2 .if (a_bitcount > 0) & (b_bitcount > 0)
2 FIRST_BIT_NUM amask, bitn_a
TMS320C6x COFF Assembler Version 4.00 Fri Feb 16 15:51:02 2001
Copyright (c) 1996-2000 Texas Instruments Incorporated
dss_aisr.s62 PAGE 17
2 FIRST_BIT_NUM bmask, bitn_b
2 .eval amask & ~(1 << bitn_a), amask
2 .eval bmask & ~(1 << bitn_b), bmask
2
2 .if !(((a_bitcount = 1) & (b_bitcount > 2)) | ((b_bitcount = 1) & (a_bitcount > 2)
2 ;
2 ; At this point, one of the following is true:
2 ; 1. a_bitcount & b_bitcount > 1
2 ; 2. a_bitcount & b_bitcount = 1
2 ; 3. a_bitcount = 1 & b_bitcount = 2
2 ; 4. a_bitcount = 2 & b_bitcount = 1
2 ; In cases 2-4 this is the last iteration of the loop
2 ;
2
2 stw b:bitn_b:, *+SPB[offset] ; CODE
2 || stw a:bitn_a:, *+SPA[offset - 1] ; CODE
2
2 .eval offset - 2, offset
2 .eval a_bitcount - 1, a_bitcount
2 .eval b_bitcount - 1, b_bitcount
2 .else
2 ;
2 ; Either a_bitcount or b_bitcount equals 1, but not both.
2 ; The one != 1 is > 2.
2 ; We're going to exit the loop after this, knowing we'll
2 ; also be doing the next loop at least twice.
2 ;
2 .if (b_bitcount = 1)
2 .asg amask, mask
2 .asg A, reg
2 .asg TMPB, tmpreg
2 .elseif (a_bitcount = 1)
2 .asg bmask, mask
2 .asg B, reg
2 .asg TMPA, tmpreg
2 .else
2 .emsg "Bad macro logic"
2 .break
2 .endif
2
2 FIRST_BIT_NUM mask, bitn_next
2
2 stw b:bitn_b:, *+SPB[offset] ; CODE
2 || stw a:bitn_a:, *+SPA[offset - 1] ; CODE
2 || mv :reg::bitn_next:, tmpreg ; CODE
2
2 .eval offset - 2, offset
2 .eval a_bitcount - 1, a_bitcount
2 .eval b_bitcount - 1, b_bitcount
2
2 .break
2 .endif
2 .else
2 .break
2 .endif
TMS320C6x COFF Assembler Version 4.00 Fri Feb 16 15:51:02 2001
Copyright (c) 1996-2000 Texas Instruments Incorporated
dss_aisr.s62 PAGE 18
2 .endloop
3 .if (6 > 0) & (5 > 0)
3 000001e8 FIRST_BIT_NUM amask, bitn_a
4 .asg 0, BITNUM
4 .eval 1008, regmask
5 .if (1008 & 1)
5 .break
5 .endif
5 .eval 1008 >> 1, regmask
5 .eval 0 + 1, BITNUM
5 .if (504 & 1)
5 .break
5 .endif
5 .eval 504 >> 1, regmask
5 .eval 1 + 1, BITNUM
5 .if (252 & 1)
5 .break
5 .endif
5 .eval 252 >> 1, regmask
5 .eval 2 + 1, BITNUM
5 .if (126 & 1)
5 .break
5 .endif
5 .eval 126 >> 1, regmask
5 .eval 3 + 1, BITNUM
5 .if (63 & 1)
5 .break
3 000001e8 FIRST_BIT_NUM bmask, bitn_b
4 .asg 0, BITNUM
4 .eval 992, regmask
5 .if (992 & 1)
5 .break
5 .endif
5 .eval 992 >> 1, regmask
5 .eval 0 + 1, BITNUM
5 .if (496 & 1)
5 .break
5 .endif
5 .eval 496 >> 1, regmask
5 .eval 1 + 1, BITNUM
5 .if (248 & 1)
5 .break
5 .endif
5 .eval 248 >> 1, regmask
5 .eval 2 + 1, BITNUM
5 .if (124 & 1)
5 .break
5 .endif
5 .eval 124 >> 1, regmask
5 .eval 3 + 1, BITNUM
5 .if (62 & 1)
5 .break
5 .endif
5 .eval 62 >> 1, regmask
5 .eval 4 + 1, BITNUM
TMS320C6x COFF Assembler Version 4.00 Fri Feb 16 15:51:02 2001
Copyright (c) 1996-2000 Texas Instruments Incorporated
dss_aisr.s62 PAGE 19
5 .if (31 & 1)
5 .break
3 .eval 1008 &⌨️ 快捷键说明
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