📄 dss_aisr.lst
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4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
TMS320C6x COFF Assembler Version 4.00 Fri Feb 16 15:51:02 2001
Copyright (c) 1996-2000 Texas Instruments Incorporated
dss_aisr.s62 PAGE 12
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
TMS320C6x COFF Assembler Version 4.00 Fri Feb 16 15:51:02 2001
Copyright (c) 1996-2000 Texas Instruments Incorporated
dss_aisr.s62 PAGE 13
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
2
2 ; make sure at least two A registers are specified
2 .if (8 = 0)
2 .eval C62_A0 | C62_A1, amask
2 .eval a_bitcount + 2, a_bitcount
2 .elseif (8 = 1)
2 .if (amask & C62_A0)
2 .eval amask | C62_A1, amask
2 .eval a_bitcount + 1, a_bitcount
2 .else
TMS320C6x COFF Assembler Version 4.00 Fri Feb 16 15:51:02 2001
Copyright (c) 1996-2000 Texas Instruments Incorporated
dss_aisr.s62 PAGE 14
2 .eval amask | C62_A0, amask
2 .eval a_bitcount + 1, a_bitcount
2 .endif
2 .endif
2
2 ; make sure at least one B register is specified
2 .if (1008 = 0)
2 .eval (C62_B0 >> 16) & 0xffff, bmask
2 .eval b_bitcount + 1, b_bitcount
2 .endif
2
2 .eval 8 + 6 + 0, ones
2
2 .eval 14 + 1, tmp_ones ; align to even
2 .eval 15 & 0xfffffffe, even_ones ; number of words
2 .eval 14 * 4, words
2 .eval 14 - 1, offset
2
2 ; assign A-side stack frame pointer and temp A register
2 000001d4 FIRST_BIT_NUM amask, bitn_a
3 .asg 0, BITNUM
3 .eval 1020, regmask
3 .loop 32
3 .if (regmask & 1)
3 .break
3 .endif
3 .eval regmask >> 1, regmask
3 .eval BITNUM + 1, BITNUM
3 .endloop
4 .if (1020 & 1)
4 .break
4 .endif
4 .eval 1020 >> 1, regmask
4 .eval 0 + 1, BITNUM
4 .if (510 & 1)
4 .break
4 .endif
4 .eval 510 >> 1, regmask
4 .eval 1 + 1, BITNUM
4 .if (255 & 1)
4 .break
2 .eval 1020 & ~(1 << 2), amask
2 .asg a2, SPA
2 000001d4 FIRST_BIT_NUM amask, bitn_a
3 .asg 0, BITNUM
3 .eval 1016, regmask
3 .loop 32
3 .if (regmask & 1)
3 .break
3 .endif
3 .eval regmask >> 1, regmask
3 .eval BITNUM + 1, BITNUM
3 .endloop
4 .if (1016 & 1)
4 .break
TMS320C6x COFF Assembler Version 4.00 Fri Feb 16 15:51:02 2001
Copyright (c) 1996-2000 Texas Instruments Incorporated
dss_aisr.s62 PAGE 15
4 .endif
4 .eval 1016 >> 1, regmask
4 .eval 0 + 1, BITNUM
4 .if (508 & 1)
4 .break
4 .endif
4 .eval 508 >> 1, regmask
4 .eval 1 + 1, BITNUM
4 .if (254 & 1)
4 .break
4 .endif
4 .eval 254 >> 1, regmask
4 .eval 2 + 1, BITNUM
4 .if (127 & 1)
4 .break
2 .eval 1016 & ~(1 << 3), amask
2 .asg a3, TMPA
2 .eval 8 - 2, a_bitcount
2
2 ; assign B-side stack frame pointer and temp B register
2 000001d4 FIRST_BIT_NUM bmask, bitn_b
3 .asg 0, BITNUM
3 .eval 1008, regmask
3 .loop 32
3 .if (regmask & 1)
3 .break
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