📄 dss_aisr.lst
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2
2 ; Save ISR registers
2 0000012c 07BD9DC2 subaw SP, HWI_NUMSTK, SP
2 00000130 003D42F5 stw a0, *+SP[HWI_STKA0] ; save A0
2 00000134 003C11A0 || mv SP, a0 ; setup A-side stack pointer
2
2 00000140 003CA2F7 stw b0, *+SP[HWI_STKB0] ; B-side temp register save
2 00000144 00802275 || stw a1, *+a0[HWI_STKA1] ; A-side temp register save
2 00000148 008411A1 || mv b1, a1 ; setup B-side temp save
2 0000014c 009803E2 || mvc irp, b1 ; Save IRP return address
2
2 00000150 00808275 stw a1, *+a0[HWI_STKB1] ; actual save of B1
2 00000154 00BD02F7 || stw b1, *+SP[HWI_STKIRP] ; Save IRP/NRP return addr
2 00000158 008811A1 || mv b2, a1 ; setup B-side temp save
2 0000015c 010003E2 || mvc amr, b2 ; setup AMR save
2
2 00000160 01BC42F7 stw b3, *+SP[HWI_STKB3] ; save B3 return register
2 00000164 00806275 || stw a1, *+a0[HWI_STKB2] ; actual save of B2
2 00000168 008811A1 || mv b2, a1 ; setup AMR save
2 0000016c 007FFFAA || mvkl 0xffff, b0 ; setup mask
2
2 00000170 0080E275 stw a1, *+a0[HWI_STKAMR] ; actual save of AMR
TMS320C6x COFF Assembler Version 4.00 Fri Feb 16 15:51:02 2001
Copyright (c) 1996-2000 Texas Instruments Incorporated
dss_aisr.s62 PAGE 5
2 00000174 073CC2F7 || stw DP, *+SP[HWI_STKDP]
2 00000178 010420FB || zero b2 ; setup for AMR set
2 0000017c 0000006A || mvkh 0xffff, b0 ; setup mask
2
2 00000180 0700002A! mvkl $bss, DP
2 00000184 0700006A! mvkh $bss, DP
2
2 00000188 000803A3 mvc b2, amr ; AMR = 0
2 0000018c 0080006C! || ldw *+DP(SWI_D_lock), a1 ; load SWI_D_lock
2
2 ; Disable maskable interrupts (no effect for NMIE)
2
2 .if (0 = 0)
2 00000190 0100006E! ldw *+DP(HWI_D_ccmask), b2 ; load HWI_D_ccmask
2 .else
2 .var CCMASKVAL
2 .asg 0, CCMASKVAL
2 .eval :CCMASK:, CCMASKVAL
2 mvk :CCMASKVAL:, b2 ; use the CCMASK value
2 .endif
2
2 00000194 019003E3 mvc ier, b3 ; get current IER
2 00000198 0003EDDA || xor -1, b0, b0 ; flip mask bits
2
2 000001a0 008C0F7B and b0, b3, b1 ; disable IEMASK bits
2 000001a4 000403E2 || mvc csr, b0 ; get CSR
2
2 000001a8 020403A3 mvc b1, ier ; set new IER
2 000001ac 003D22F7 || stw b0, *+SP[HWI_STKCSR] ; save CSR
2 000001b0 00002FDA || or GIE, b0, b0 ; turn on GIE of CSR
2
2 000001b4 00807E2B mvk C62_CCFIELDS, b1
2 000001b8 008421A0 || add a1, 1, a1 ; a1 = SWI_D_lock + 1
2 000001bc 008027E2 and b1, b0, b1 ; extract pcc+dcc fields of csr
2 000001c0 000022E2 xor b1, b0, b0 ; clear pcc+dcc fields of csr
2
2 000001c4 0080007D! stw a1, *+DP(SWI_D_lock) ; SWI_D_lock++
2 000001c8 000046E2 || or b2, b0, b0 ; change pcc and dcc fields
2
2
2 000001cc 008003A2 mvc b0, csr ; globally enable interrupts
2 ; to allow nested interrupts
2
2 000001d0 01BC54F6 stw b3, *SP--[2] ; save old IER
2
1 ; Save user registers (except ISR registers)
1 000001d4 C62_save C62_ABTEMPS & ~(C62_ISRAB), 0 & ~(C62_ISRC)
2 .asg 0, mask
2 .asg 0, bitn_a
2 .asg 0, bitn_b
2 .asg -1, bitn_c
2 .asg 0, bitn_0
2 .asg 0, bitn_1
2 .asg 0, bitn_next
2 .asg 0, bitcount
TMS320C6x COFF Assembler Version 4.00 Fri Feb 16 15:51:02 2001
Copyright (c) 1996-2000 Texas Instruments Incorporated
dss_aisr.s62 PAGE 6
2 .asg 0, a_bitcount
2 .asg 0, b_bitcount
2 .asg 0, c_bitcount
2 .asg 0, creg0
2 .asg 0, creg1
2 .asg 0, creg_next
2
2 .eval C62_ABTEMPS & ~(C62_ISRAB) & 0x0000ffff, amask
2 .eval (C62_ABTEMPS & ~(C62_ISRAB) >> 16) & 0xffff, bmask
2 .eval 1008 & ~(C62_B15 >> 16), bmask ; don't save B15
2 .eval 0 & ~(C62_ISRC), cmask
2
2 .if (1020 = 0) & (1008 = 0) & (0 = 0)
2 .mexit
2 .endif
2
2 ;
2 ; Count 1 bits in masks
2 ;
2 000001d4 NUM_BITS amask, a_bitcount
3 .asg 0, BITCOUNT
3 .eval 1020, regmask
3 .loop 32
3 .if (regmask & 1)
3 .eval BITCOUNT + 1, BITCOUNT
3 .endif
3 .eval regmask >> 1, regmask
3 .endloop
4 .if (1020 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 1020 >> 1, regmask
4 .if (510 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 510 >> 1, regmask
4 .if (255 & 1)
4 .eval 0 + 1, BITCOUNT
4 .endif
4 .eval 255 >> 1, regmask
4 .if (127 & 1)
4 .eval 1 + 1, BITCOUNT
4 .endif
4 .eval 127 >> 1, regmask
4 .if (63 & 1)
4 .eval 2 + 1, BITCOUNT
4 .endif
4 .eval 63 >> 1, regmask
4 .if (31 & 1)
4 .eval 3 + 1, BITCOUNT
4 .endif
4 .eval 31 >> 1, regmask
4 .if (15 & 1)
4 .eval 4 + 1, BITCOUNT
4 .endif
TMS320C6x COFF Assembler Version 4.00 Fri Feb 16 15:51:02 2001
Copyright (c) 1996-2000 Texas Instruments Incorporated
dss_aisr.s62 PAGE 7
4 .eval 15 >> 1, regmask
4 .if (7 & 1)
4 .eval 5 + 1, BITCOUNT
4 .endif
4 .eval 7 >> 1, regmask
4 .if (3 & 1)
4 .eval 6 + 1, BITCOUNT
4 .endif
4 .eval 3 >> 1, regmask
4 .if (1 & 1)
4 .eval 7 + 1, BITCOUNT
4 .endif
4 .eval 1 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
TMS320C6x COFF Assembler Version 4.00 Fri Feb 16 15:51:02 2001
Copyright (c) 1996-2000 Texas Instruments Incorporated
dss_aisr.s62 PAGE 8
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
4 .eval BITCOUNT + 1, BITCOUNT
4 .endif
4 .eval 0 >> 1, regmask
4 .if (0 & 1)
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