📄 dss_aisr.lst
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TMS320C6x COFF Assembler Version 4.00 Fri Feb 16 15:51:02 2001
Copyright (c) 1996-2000 Texas Instruments Incorporated
dss_aisr.s62 PAGE 1
1 ;
2 ; Copyright 2000 by Texas Instruments Incorporated.
3 ; All rights reserved. Property of Texas Instruments Incorporated.
4 ; Restricted rights to use, duplicate or disclose this code are
5 ; granted through contract.
6 ; U.S. Patent Nos. 5,283,900 5,392,448
7 ;
8 ; "@(#) DSP/BIOS 4.00 03-27-00 (barracuda-e08)"
9 ;
10 ; ======== dss_aisr.s62 ========
11 ;
12 .include c62.h62
A 1233
13 .include hwi.h62
14 .include pip.h62
V 599
15
16 .include dss.h62
17
18
19 018C0000 DRR .set 0x018c0000 ; Data Receive Register McBSP 0
20 018C0004 DXR .set 0x018c0004 ; Data Transmit Register McBSP 0
21
22
23 00000000 .bss rtxDone,4,4 ; Allocate temp variable in .bss to
24 ; allow loads via b14. No cinit record
25 ; needed because ISR writes to this
26 ; location before it reads it.
27 00000000 .text
28
29 .global _DSS_isr, rtxDone, rxErr, txErr
30
31 ;
32 ; ====== _DSS_aisr ======
33 ;
34 00000000 _DSS_isr:
35
36 00000000 003C54F4 stw a0,*b15--[2] ; push temp registers
37 00000004 00BC54F4 stw a1,*b15--[2]
38 00000008 013C54F4 stw a2,*b15--[2]
39 0000000c 00BC54F6 stw b1,*b15--[2]
40 00000010 013C54F6 stw b2,*b15--[2]
41
42 ; rxDone = 0, txDone = 0
43 00000014 010005E0 zero a2
44
45 ; if (DSS_rxCnt) {
46 00000018 0080006E! ldw *+b14(_DSS_rxCnt),b1
47 0000001c 00006000 nop 4
48
49 00000020 50007C92 [!b1] b rxErr ; process rx error
50
51 ; *DSS_rxPtr++ = *DRR;
52 00000024 40800028 [b1] mvkl DRR,a1 ; load address of serial port DRR
53 00000028 4080C668 [b1] mvkh DRR,a1
TMS320C6x COFF Assembler Version 4.00 Fri Feb 16 15:51:02 2001
Copyright (c) 1996-2000 Texas Instruments Incorporated
dss_aisr.s62 PAGE 2
54 0000002c 40840265 [b1] ldw *a1,a1 ; read word from DRR
55 00000030 4080006E! ||[b1] ldw *+b14(_DSS_rxPtr),b1 ; load DSS_rxPtr
56 00000034 4100006E! [b1] ldw *+b14(_DSS_rxCnt),b2 ; load DSS_rxCnt
57 00000038 00004000 nop 3
58 0000003c 008436F4 stw a1,*b1++ ; store DRR at *DSS_rxPtr, auto
59 ; increment DSS_rxPtr
60 00000040 0080007E! stw b1,*+b14(_DSS_rxPtr) ; store updated DSS_rxPtr
61
62 ; DSS_rxCnt--;
63 00000044 010BE1A2 sub b2,1,b2 ; decrement DSS_rxCnt
64 00000048 0100007E! stw b2,*+b14(_DSS_rxCnt) ; store updated DSS_rxCnt
65
66 ; if (DSS_rxCnt == 0) {
67 ; rxDone = 1;
68 ; }
69 ; }
70 0000004c 710000A8 [!b2] mvk 1,a2
71
72 00000050 checkTx:
73
74 ; if (DSS_txCnt) {
75 00000050 0080006E! ldw *+b14(_DSS_txCnt),b1
76 00000054 00006000 nop 4
77
78 00000058 50007C92 [!b1] b txErr ; process tx error
79
80 ; *DXR = *DSS_txPtr++;
81 0000005c 4080006E! [b1] ldw *+b14(_DSS_txPtr),b1 ; load DSS_txPtr
82 00000060 4100006E! [b1] ldw *+b14(_DSS_txCnt),b2 ; load DSS_txCnt
83 00000064 00004000 nop 3
84
85 00000068 000436E4 ldw *b1++,a0 ; load word pointed to by DSS_txPtr
86 ; autoincrement DSS_txPtr
87 0000006c 0080007E! stw b1,*+b14(_DSS_txPtr) ; store updated DSS_txPtr
88
89 00000070 00800228 mvkl DXR,a1 ; load address of serial port DXR
90 00000074 0080C668 mvkh DXR,a1
91
92
93 ; DSS_txCnt--;
94 00000078 010BE1A2 sub b2,1,b2 ; decrement DSS_txCnt
95
96 0000007c 00000000 nop ; wait for 'ldw' (above) to complete
97 00000080 0003C7A0 and 0xfffffffe,a0,a0 ; clear lsb to avoid AIC reprogram
98
99 00000084 00040274 stw a0,*a1 ; write word to DXR
100
101 00000088 0100007E! stw b2,*+b14(_DSS_txCnt) ; store updated DSS_txCnt
102
103 ; if (DSS_txCnt == 0) {
104 ; txDone = 1;
105 ; }
106 ; }
107 0000008c 710846A0 [!b2] or 2,a2,a2
108
TMS320C6x COFF Assembler Version 4.00 Fri Feb 16 15:51:02 2001
Copyright (c) 1996-2000 Texas Instruments Incorporated
dss_aisr.s62 PAGE 3
109
110 00000090 checkDn:
111
112 ; if ((rxDone | txDone) == 0) {
113 00000090 A0000692 [a2] b Done ; if rxDone or txDone do Done processing
114 00000094 0100007C- stw a2,*+b14(rtxDone) ; store done flags into memory
115
116 ; return; /* return from interrupt */
117 ; }
118
119 00000098 B13C52E6 [!a2] ldw *++b15[2],b2 ; restore temp registers
120 0000009c B0BC52E6 [!a2] ldw *++b15[2],b1
121 000000a0 B13C52E4 [!a2] ldw *++b15[2],a2
122 000000a4 B0BC52E4 [!a2] ldw *++b15[2],a1
123 000000a8 001800E2 b irp ; return from interrupt
124 000000ac 003C52E4 ldw *++b15[2],a0
125 000000b0 00006000 nop 4
126
127
128 000000b4 Done:
129 000000b4 013C52E6 ldw *++b15[2],b2 ; restore temp registers
130 000000b8 00BC52E6 ldw *++b15[2],b1
131 000000bc 013C52E4 ldw *++b15[2],a2
132 000000c0 00BC52E4 ldw *++b15[2],a1
133 000000c4 003C52E4 ldw *++b15[2],a0
134 000000c8 00006000 nop 4
135
136 000000cc HWI_enter C62_ABTEMPS, 0, 0xffff, 0
1
1 000000cc HWI_enter_body IEMASK, CCMASK
2
2 000000cc CHK_nargs "HWI_enter", CCMASK
2 .if ($symcmp("", "error") = 0)
2 .emsg "HWI_enter CCMASK error"
2 .endif
2
2 ; Note: global interrupts disabled by C62xx on entry into ISR
2
2 ;
2 ; Handle switchover to ISR stack.
2 ;
2 ; WARNING: The following code has a few cases of software
2 ; pipelining, where a register is loaded with 'ldw' but the
2 ; old (pre-ldw) value is still used in the 'ldw' latency
2 ; slots.
2 ;
2 000000cc 003C54F7 stw b0, *SP--[2]
2 000000d0 0000002A! || mvkl _HWI_STKBOTTOM, b0 ; highest address
2 000000d4 00BC22F7 stw b1, *+SP[1]
2 000000d8 0000006A! || mvkh _HWI_STKBOTTOM, b0
2
2 000000dc 0001E8FA cmpgt SP, b0, b0
2 000000e0 20000612 [ b0] b notOnHWIStack?
2 000000e4 3080002A! [!b0] mvkl _HWI_STKTOP, b1 ; lowest address
2 000000e8 3080006A! [!b0] mvkh _HWI_STKTOP, b1
TMS320C6x COFF Assembler Version 4.00 Fri Feb 16 15:51:02 2001
Copyright (c) 1996-2000 Texas Instruments Incorporated
dss_aisr.s62 PAGE 4
2 000000ec 3085EAFA [!b0] cmplt SP, b1, b1
2 000000f0 20BC01A2 [ b0] mv SP, b1 ; old b0 can be used safely here
2 000000f4 27BC5D42 [ b0] addaw SP, 2, SP ; 2 = # words alloced by us
2
2 000000f8 50000992 [!b1] b onHWIStack?
2 000000fc 50BC22E6 [!b1] ldw *+SP[1], b1 ; old b1 can be used for 4 more cycles
2 00000100 503C52E6 [!b1] ldw *++SP[2], b0 ; ld early, b0 used 3 cycles after br
2 00000104 00002000 nop 2
2 00000108 40BC01A3 [ b1] mv SP, b1
2 0000010c 47BC5D42 ||[ b1] addaw SP, 2, SP ; 2 = # words alloced by us
2
2 00000110 notOnHWIStack?:
2 ;
2 ; The following operations below must be atomic:
2 ; SP = HWI_STKBOTTOM
2 ; HWI_D_spsave = SP
2 ;
2 00000110 000442E7 ldw *+b1[2], b0
2 00000114 0000002A! || mvkl _HWI_D_spsave, b0
2 00000118 008422E7 ldw *+b1[1], b1
2 0000011c 0000006A! || mvkh _HWI_D_spsave, b0
2 00000120 078002F7 stw SP, *b0 ; HWI_D_spsave = SP
2 00000124 0780002A! || mvkl _HWI_STKBOTTOM, SP
2 00000128 0780006A! mvkh _HWI_STKBOTTOM, SP
2
2 ; no delay slots necessary to wait for above ldw's to
2 ; complete since b0, b1 aren't needed below for 2 more
2 ; cycles.
2
2 0000012c onHWIStack?:
2 ;
2 ; All GP registers are in their pre-interrupt state.
2 ;
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