rom.vhd

another 8051 core porocesssor vhdl source code

--*******************************************************************       --
--IMPORTANT NOTICE                                                          --
--================                                                          --
--Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  --
--This file and associated deliverables are the trade secrets,              --
--confidential information and copyrighted works of Mentor Graphics         --
--Corporation and its licensors and are subject to your license agreement   --
--with Mentor Graphics Corporation.                                         --
--                                                                          --
--Use of these deliverables for the purpose of making silicon from an IC    --
--design is limited to the terms and conditions of your license agreement   --
--with Mentor Graphics If you have further questions please contact Mentor  --
--Graphics Customer Support.                                                --
--                                                                          --
--This Mentor Graphics core (m8051 v1999.120) was extracted on              --
--workstation hostid _hostid_ Inventra                                      --
------------------------------------------------------------------------
-- File			: 	rom.vhd
-- Author		: 	Rob Douglas
-- Library		:	WORK
-- Created on	        :	May 17th 1995
-- Purpose		:	ROM Model
-- Version		:	1.004
-- Mod_Date		:       30th March 1999
-- Mod_Hist		:       1.004 Switched to '87 standard file syntax
--                              1.003 Reports added
--                              1.002 Delay added
--                              1.001 (Original) 
------------------------------------------------------------------------
--Function of the entity : A model of the ROM has been constructed.
-- An image of ROM data may be loaded from a file comprising Intel hex records
-- called "default_rom.hex".
------------------------------------------------------------------------
Library IEEE;
Use IEEE.std_logic_1164.all;

Library std;
Use std.textio.all;

Library WORK;
Use WORK.tbs_dec.all;
------------------------------------------------------------------------
entity rom is
--*******************************************************************       --
--IMPORTANT NOTICE                                                          --
--================                                                          --
--Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  --
--This file and associated deliverables are the trade secrets,              --
--confidential information and copyrighted works of Mentor Graphics         --
--Corporation and its licensors and are subject to your license agreement   --
--with Mentor Graphics Corporation.                                         --
--                                                                          --
--Use of these deliverables for the purpose of making silicon from an IC    --
--design is limited to the terms and conditions of your license agreement   --
--with Mentor Graphics If you have further questions please contact Mentor  --
--Graphics Customer Support.                                                --
--                                                                          --
--This Mentor Graphics core (m8051 v1999.120) was extracted on              --
--workstation hostid _hostid_ Inventra                                      --
  generic( ROM_SIZE: integer := 4096;
           ROM_WIDTH: integer := 12);
  port (
	OUT_DATA: inout std_logic_vector(7 downto 0);
	Address : in std_logic_vector((ROM_WIDTH - 1) downto 0);
	NROMRD	: in std_logic;
	NCS 	: in std_logic
       );
end rom;
-------------------------------------------------------------------------------
architecture rom_RTL of rom is

type ROM_ARRAY is array (0 to ROM_SIZE-1) of byte;
signal ROM_DATA: ROM_ARRAY;
signal LoadROM : integer := 0;
    
begin

p_Load_Memory: process(LoadROM)
variable intel_data	: data_buff;
variable load_addr	: integer :=0;
variable new_line	: LINE;
variable data_length	: integer :=0;
variable good		: boolean;
variable lines_read	: integer := 0;

file HEX_FILE : text is in "default_rom.hex";                    -- '87 standard
--file HEX_FILE : text open read_mode is "default_rom.hex";      -- '93 standard

begin
  while not ENDFILE(HEX_FILE) loop
    READLINE(HEX_FILE, new_line);
    P_READ_HEX( new_line, intel_data, load_addr, data_length, good );

    for i in 1 to (data_length) loop
      ROM_DATA((load_addr) + i - 1) <= intel_data(i-1) ;
    end loop;
    LINES_READ := LINES_READ +1;
  end loop;
end process p_Load_Memory;

p_ROM_DATA_PROCESS: process(NCS, NROMRD, ADDRESS, ROM_DATA)
variable addr		: integer;
variable addr_bit 	: bit_vector((ROM_WIDTH -1) downto 0);
variable prop_del       : time := 1 ns;
begin
  if (NCS='0') and (NROMRD='0')  then
    addr_bit := To_bitvector(ADDRESS((ROM_WIDTH - 1) downto 0));
    addr := Convert_to_Int (addr_bit);
    OUT_DATA <= To_StdLogicVector (ROM_DATA(addr)) after prop_del;
  else
    OUT_DATA <= "ZZZZZZZZ" after prop_del;
  end if;
end process p_ROM_DATA_PROCESS;

end rom_RTL ;