ram.vhd

another 8051 core porocesssor vhdl source code

--*******************************************************************       --
--IMPORTANT NOTICE                                                          --
--================                                                          --
--Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  --
--This file and associated deliverables are the trade secrets,              --
--confidential information and copyrighted works of Mentor Graphics         --
--Corporation and its licensors and are subject to your license agreement   --
--with Mentor Graphics Corporation.                                         --
--                                                                          --
--Use of these deliverables for the purpose of making silicon from an IC    --
--design is limited to the terms and conditions of your license agreement   --
--with Mentor Graphics If you have further questions please contact Mentor  --
--Graphics Customer Support.                                                --
--                                                                          --
--This Mentor Graphics core (m8051 v1999.120) was extracted on              --
--workstation hostid _hostid_ Inventra                                      --
-------------------------------------------------------------------------------
-- File			: 	ram.vhd
-- Author		: 	Rob Douglas
-- Library		:	ROMRAM
-- Created on	        :	May 16th 1995
-- Purpose		:	Behavioural RAM Model
-- Version		:	1.003
-- Mod_Date		: 	30th March 1999
-- Mod_Hist		:       1.003 - switched to '87 standard file syntax
--                              1.001 May 18th 1995
-------------------------------------------------------------------------------
-- Function of the entity : A model of the RAM has been constructed.
-- An image of RAM data may be loaded from a file comprising Intel hex records
-- called "ram.hex".
-------------------------------------------------------------------------------
Library IEEE;
Use IEEE.std_logic_1164.all;

Use std.textio.all;
Use WORK.tbs_dec.all;
-------------------------------------------------------------------------------
entity  ram is
--*******************************************************************       --
--IMPORTANT NOTICE                                                          --
--================                                                          --
--Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  --
--This file and associated deliverables are the trade secrets,              --
--confidential information and copyrighted works of Mentor Graphics         --
--Corporation and its licensors and are subject to your license agreement   --
--with Mentor Graphics Corporation.                                         --
--                                                                          --
--Use of these deliverables for the purpose of making silicon from an IC    --
--design is limited to the terms and conditions of your license agreement   --
--with Mentor Graphics If you have further questions please contact Mentor  --
--Graphics Customer Support.                                                --
--                                                                          --
--This Mentor Graphics core (m8051 v1999.120) was extracted on              --
--workstation hostid _hostid_ Inventra                                      --
  port (
	DATA_IN : in std_logic_vector(7 downto 0);      
	DATA_OUT: out std_logic_vector(7 downto 0);
	Address : in std_logic_vector(7 downto 0);
	NRAWR	: in std_logic;
	NRARD	: in std_logic;
	NCS 	: in std_logic
       );
end ram;
------------------------------------------------------------------------
architecture ram_RTL of ram is
signal RAM_DATA:T_memory;
signal LoadRAM : integer := 0;
    
begin

p_RAM_DATA_PROCESS: process(NCS,NRARD,NRAWR,ADDRESS,DATA_IN, LoadRAM)
variable add		: integer;
variable add_bit 	: bit_vector(7 downto 0);
variable par_data	: data_buff;
variable load_add	: integer :=0;
variable new_line	: LINE;
variable data_len	: integer :=0;
variable good		: boolean;

file HEX_FILE : text is in "ram.hex";                     -- '87 standard
--file HEX_FILE	: text open read_mode is "ram.hex";       -- '93 standard

begin
  if LoadRAM'event then
    if ENDFILE(HEX_FILE) then
      assert not(ENDFILE(HEX_FILE)) 
      report "End of file"
      severity note;
    else
      while not ENDFILE(HEX_FILE) loop
        READLINE(HEX_FILE, new_line);
        P_READ_HEX( new_line, par_data, load_add, data_len, good );
        for i in 1 to (data_len) loop
          RAM_DATA((load_add) + i - 1) <= par_data(i-1) ;
        end loop;
      end loop;
    end if;
  else
    if (NCS='0') and (NRAWR='0')  then
	add_bit := To_bitvector(ADDRESS(7 downto 0));
	add := Convert_to_Int (add_bit);
	RAM_DATA(add) <= To_bitvector(DATA_IN);
    else
	DATA_OUT <= "ZZZZZZZZ";
    end if;
  end if;


if (NCS='0') and (NRARD='0')  then
    if(((ADDRESS(0)= '0') or (ADDRESS(0)= '1')) and ((ADDRESS(1)= '0') or (ADDRESS(1)= '1')) and 
       ((ADDRESS(2)= '0') or (ADDRESS(2)= '1')) and ((ADDRESS(3)= '0') or (ADDRESS(3)= '1')) and 
       ((ADDRESS(4)= '0') or (ADDRESS(4)= '1')) and ((ADDRESS(5)= '0') or (ADDRESS(5)= '1')) and 
       ((ADDRESS(6)= '0') or (ADDRESS(6)= '1')) and ((ADDRESS(7)= '0') or (ADDRESS(7)= '1'))) then
	add_bit := To_bitvector(ADDRESS(7 downto 0));
	add := Convert_to_Int (add_bit);
	DATA_OUT <= To_StdLogicVector (RAM_DATA(add));
    else
         DATA_OUT <="XXXXXXXX";
    end if;
else
	DATA_OUT <= "ZZZZZZZZ";
end if;
end process p_RAM_DATA_PROCESS;

end ram_RTL ;
------------------------------------------------------------------------