sim.readme

another 8051 core porocesssor vhdl source code

This is the sim.readme file for the m8051 soft core.

General
=======

A general demonstration test bench is provided in the sub-directory,
sim and is called m8051_tb.v(hd)  This testbench
may be used with either the RTL or synthesised M8051 Soft Core.
The test bench contains external stimuli for the soft core and references 
RTL models for I/O cells, internal and external memory functions.
The testbench loads an M8051 assembled test program, func1, into the
internal program memory model at the beginning of simulation.  This
test program exercises the M8051 instruction set and many peripheral functions.

Statement and branch code coverage with this testbench and the func1 assembler
code is about 97% and 94% respectively.  Almost all unexecuted statements are
RTL X-handlers.

Simulation Shell Scripts
========================

This directory contains two shell scripts, msim.scr and vxl.scr, for running
the customer-deliverable testbench simulation of m8051 at RTL and
synthesised gate-level using the Modelsim 5.2d simulator or VerilogXL. Both
simulators generate a tabular listing file of results,

Both scripts may take the same optional arguments:

msim.scr [-c] [-g] - For Modelsim
vxl.scr  [-c] [-g] - for VerilogXL

-c  causes simulation to be run in command line mode, i.e. without a GUI.
    By default a GUI session is started.

-g  causes a gate-level simulation to be run, using a Verilog netlist and SDF
    file.  The default is to compile and simulate the RTL.

Simulation takes place with the contents of the Verilog memory file
default_rom.rom loaded in the program memory model, rom.v  (for Verilog) or
the hex record file default_rom.hex loaded in the model, rom.vhd (for VHDL).

Simulation generates a listing that is written to the file m8051uni.lis together
with a log file named as follows:

msim_rtl.log   - Modelsim RTL simulation log file;
msim_gate.log  - Modelsim netlist simulation log file;
vxl_rtl.log    - VerilogXL RTL simulation log file;
vxl_gate.log   - VerilogXL netlist simulation log file;

See below for language-specific details of running the script.

Running VHDL Simulations
========================

Simulations have been carried out using Mentor Modelsim. In
order to do so the working sub-directory vhdl/sim/work is
created to store the compiled model. The script msim.scr in the vhdl/sim
subdirectory should be run in the vhdl/sim directory.
This creates the sub-directory work and into it compiles the M8051 RTL
source files from the rtl subdirectory or a netlist from gates/synop
sub-directory and testbench files from the vhdl/sim
directory.  The script sets out the correct order for compilation of this
hierarchical design.

Link files are used for referencing program and data memory 
contents. One of these links is called default_rom.hex which
should be either a pointer to or a copy of func1.hex, which is the 
deliverable assembler test program code in Intel hex record format.
The second link is called ram.hex and may optionally point to a file
containing initial contents for the internal data memory.  As
delivered, this link is a file of zero length.

The script msim.scr then runs the Mentor Modelsim simulator.  This runs
742 us of simulation time using an input clock period of 20 ns and produces
two simulation listing files, m8051uni.lis and m8051bir.lis. 
m8051uni.lis contains a listing for each signal at the Soft Core
top-level boundary, i.e. the unidirectional signals listed in the
M8051 Product Specification.   m8051bir.lis contains a listing for the I/O pads
of bidirectional cells in the testbench giving a listing which corresponds
to the pins found on the original device.

Gate-level simulations have been run using Mentor Modelsim on a netlist
synthesised from the RTL by Synopsys Design Compiler.  Simulation
uses an SDF file containing pre-layout delay estimates. Timing violation
warnings for vector 1 have been seen and can be ignored.

Gate level simulations can be run using the option -g as an argument to the
script msim.scr.  The script compiles the synthesised netlist file, m8051.vhd,
and SDF file, m8051.sdf
from the vhdl/gates/synop directory.  The script runs the Mentor Modelsim
simulator referencing the SDF file.

The VHDL testbench is self-checking against the reference files
m8051uni.ref and m8051bir.ref.  Any difference from the reference
results is logged at run time in the corresponding fault file
m8051uni.flt or m8051bir.flt.  Typically, gate level simulations
contain some failures for vector number 1 only.  These are acceptable
simulator initialisation differences.

 
Running Verilog Simulations
============================

Simulations have been carried using Mentor Modelsim. In
order to so the working sub-directory verilog/sim/work is
created. The script msim.scr in the verilog/sim
subdirectory should be run in the verilog/sim directory.  This creates the
sub-directory work and into it compiles the
M8051 Verilog RTL source files from verilog/rtl or netlist from gates/synop 
and testbench files from the verilog/sim directory.  The compile script sets
out the correct order for compilation of this hierarchical design.

A link file called default_rom.rom is created by the script for referencing
program memory contents in a Verilog-readable format.  This file should
be either a link or copy of the file func1.rom, which is the 
deliverable assembler test program code in Verilog readable format.
Optionally a link called ram.rom may point to a file
containing initial contents for the internal data memory.  This is not
implemented in the deliverables.

Files in the Verilog readable format may be generated from the
corresponding Intel hex record (.hex file) using the the Mentor  
utility hex2rom8 which performs the text format conversion.  This
program is compiled to run under Solaris on Sun Sparc stations.

With the RTL compiled and the program code linked, the script then runs the
Modelsim simulator.  This executes 742 us of simulation time using an input
clock period of 20 ns and produces
two simulation listing files, m8051uni.lis and m8051bir.lis. 
m8051uni.lis contains a listing for each signal at the Soft Core
top-level boundary, i.e. the unidirectional signals listed in the
M8051 Product Specification.   m8051bir.lis contains a listing for the I/O pads
of bidirectional cells in the testbench giving a listing which corresponds
to the pins found on the original device.

Gate-level simulations have been run using Mentor Modelsim on a netlist
synthesised from the RTL by Synopsys Design Compiler.  Simulation
uses an SDF file containing pre-layout delay estimates. Timing
violation warnings for vector 1 have been seen and can be ignored.

Gate level simulations can be run using the option -g with the script msim.scr
(or vxl.scr) to compile and simulate the synthesised netlist file, m8051.v,
and SDF file, m8051.sdf, from the verilog/gates/synop directory. 

The Verilog version of the test bench is not self-checking.  Instead
simulation results are verified by comparing the m8051uni.lis file
with the reference file vhdl/sim/m8051uni.ref  This is
performed using a UNIX diff command in the run script msim.scr
The file m8051.rtl.diff (RTL) or m8051.gates.diff (netlist) may acceptably
contain differences for vector number 1.