io_buffer.vhd

another 8051 core porocesssor vhdl source code

--*******************************************************************       --
--IMPORTANT NOTICE                                                          --
--================                                                          --
--Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  --
--This file and associated deliverables are the trade secrets,              --
--confidential information and copyrighted works of Mentor Graphics         --
--Corporation and its licensors and are subject to your license agreement   --
--with Mentor Graphics Corporation.                                         --
--                                                                          --
--Use of these deliverables for the purpose of making silicon from an IC    --
--design is limited to the terms and conditions of your license agreement   --
--with Mentor Graphics If you have further questions please contact Mentor  --
--Graphics Customer Support.                                                --
--                                                                          --
--This Mentor Graphics core (m8051 v1999.120) was extracted on              --
--workstation hostid _hostid_ Inventra                                      --
-- io_buffer.vhd-using "cells"
-- (c) Copyright Mentor Graphics Corporation 1997.  All rights reserved.
-- Version 2.000

-- Version 2.000 14.iv.97 RPD:  Input buffers added to MD and FI inputs
--               to prevent Z's propagating into RTL model of design.
-- Version 1.002 Pullup removed from P0 
-- Version 1.001 Original

---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
------------------------------------------------------------------------

entity io_buffer is
--*******************************************************************       --
--IMPORTANT NOTICE                                                          --
--================                                                          --
--Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  --
--This file and associated deliverables are the trade secrets,              --
--confidential information and copyrighted works of Mentor Graphics         --
--Corporation and its licensors and are subject to your license agreement   --
--with Mentor Graphics Corporation.                                         --
--                                                                          --
--Use of these deliverables for the purpose of making silicon from an IC    --
--design is limited to the terms and conditions of your license agreement   --
--with Mentor Graphics If you have further questions please contact Mentor  --
--Graphics Customer Support.                                                --
--                                                                          --
--This Mentor Graphics core (m8051 v1999.120) was extracted on              --
--workstation hostid _hostid_ Inventra                                      --
  port (
	P0_I, P1_I, P2_I, P3_I:     out std_logic_vector(7 downto 0);
	BUFF_FI, BUFF_MD:           out std_logic_vector(7 downto 0);
        ALEI, PSEI:                 out std_logic;
	P0_OI, P1_OI, P2_OI, P3_OI: in std_logic_vector(7 downto 0);
	P0_C, P1_C, P2_C, P3_C:     in std_logic_vector(7 downto 0);
	FI_INPUT, MD_INPUT:         in std_logic_vector(7 downto 0);
        ALEO, NPSEN, NALEN:         in std_logic;
	P0, P1, P2, P3:             inout std_logic_vector(7 downto 0);
        ALE, PSEN:                  inout std_logic
	);
end io_buffer;

------------------------------------------------------------------------
architecture RTL of io_buffer is
------------------------------------------------------------------------
procedure INPUT_BUFFER (signal A: in std_logic_vector;
                        signal Y: out std_logic_vector ) is
begin
   for I in 0 to 7 loop
      case A(I) is
          when '0'    => Y(I) <= '0';
          when 'L'    => Y(I) <= '0';
          when '1'    => Y(I) <= '1';
          when 'H'    => Y(I) <= '1';
          when others => Y(I) <= 'X';
      end case;
   end loop;
end INPUT_BUFFER;

procedure INPUT_CELL (signal A: in std_logic;
                      signal Y: out std_logic ) is
begin
   case A is
      when '0'    => Y <= '0';
      when 'L'    => Y <= '0';
      when '1'    => Y <= '1';
      when 'H'    => Y <= '1';
      when others => Y <= 'X';
   end case;
end INPUT_CELL;

-- True tri-state output buffer for port 0, output goes high-Z when off.
procedure TRISTATE_BUFFER (signal A, B: in std_logic_vector;
                           signal Y: out std_logic_vector) is
begin
   for I in 0 to 7 loop
      case B(I) is
          when '0'    => Y(I) <= A(I);
          when 'L'    => Y(I) <= A(I);
          when '1'    => Y(I) <= 'Z';
          when 'H'    => Y(I) <= 'Z';
          when others => Y(I) <= 'X';
      end case;
   end loop;
end TRISTATE_BUFFER;

-- Output buffer for ports 1 to 3, output goes weakly high when off.
procedure PULL_UP_BUFFER (signal A, B: in std_logic_vector;
                          signal Y: out std_logic_vector(7 downto 0)) is
begin
   for I in 0 to 7 loop
      case B(I) is
          when '0'    => Y(I) <= A(I);
          when 'L'    => Y(I) <= A(I);
          when '1'    => Y(I) <= 'H';
          when 'H'    => Y(I) <= 'H';
          when others => Y(I) <= 'X';
      end case;
   end loop;
end PULL_UP_BUFFER;

procedure PULL_UP_CELL (signal A, B: in std_logic;
                        signal Y: out std_logic   ) is
begin
   case B is
      when '0'    => Y <= A;
      when 'L'    => Y <= A;
      when '1'    => Y <= 'H';
      when 'H'    => Y <= 'H';
      when others => Y <= 'X';
   end case;
end PULL_UP_CELL;

begin

-- Tri-state output buffers for ports 0 to 3.

output_p0: process(P0_OI, P0_C)
begin
   TRISTATE_BUFFER(P0_OI, P0_C, P0);
end process output_p0;

output_p1: process(P1_OI, P1_C)
begin
   PULL_UP_BUFFER(P1_OI, P1_C, P1);
end process output_p1;

output_p2: process(P2_OI, P2_C)
begin
   PULL_UP_BUFFER(P2_OI, P2_C, P2);
end process output_p2;

output_p3: process(P3_OI, P3_C)
begin
   PULL_UP_BUFFER(P3_OI, P3_C, P3);
end process output_p3;

output_ale: process(ALEO, NPSEN, NALEN)
begin
   PULL_UP_CELL(ALEO, NALEN, ALE);
   PULL_UP_CELL(NPSEN, NALEN, PSEN);
end process output_ale;

-- Simple input buffers to stop Z's propagating through RTL macro.

buffer_P0: process(P0)
begin
   INPUT_BUFFER(P0, P0_I);
end process buffer_P0;

buffer_P1: process(P1)
begin
   INPUT_BUFFER(P1, P1_I);
end process buffer_P1;

buffer_P2: process(P2)
begin
   INPUT_BUFFER(P2, P2_I);
end process buffer_P2;

buffer_P3: process(P3)
begin
   INPUT_BUFFER(P3, P3_I);
end process buffer_P3;

buffer_MD: process(MD_INPUT)
begin
   INPUT_BUFFER(MD_INPUT, BUFF_MD);
end process buffer_MD;

buffer_FI: process(FI_INPUT)
begin
   INPUT_BUFFER(FI_INPUT, BUFF_FI);
end process buffer_FI;

buffer_ale: process(ALE, PSEN)
begin
   INPUT_CELL(ALE, ALEI);
   INPUT_CELL(PSEN, PSEI);
end process buffer_ale;

------------------------------------------------------------
end RTL;