m8051_tb.vhd

another 8051 core porocesssor vhdl source code

   );
--*********************************************************************
U3:rom
port map(
   OUT_DATA(7 downto 0) => MD_INPUT(7 downto 0),
   Address => M(11 downto 0),
   NCS => unused0,
   NROMRD => NMOE
   );
--*********************************************************************
U4:ram
   port map(
   DATA_OUT(7 downto 0) => RAM_DATA(7 downto 0),
   Address => FA(7 downto 0),
   DATA_IN(7 downto 0) => FO(7 downto 0),
   NRAWR => NFWE,
   NRARD => NFOE,
   NCS =>unused0
   );
--*********************************************************************
U7:ram
-- external RAM model for MOVX instructions, disabled during download
-- mode in order to avoid port 0 contentions.
port map(
   DATA_OUT(7 downto 0) => P0(7 downto 0),
   Address => EXT_ADDR(7 downto 0),
   DATA_IN(7 downto 0) => P0(7 downto 0),
   NRAWR => P3(6),
   NRARD => P3(7),
   NCS => DLM
   );
--*********************************************************************
unused1 <= '1';
unused0 <= '0';
--*********************************************************************
-- Test Bench starts here.
--*********************************************************************

-- Initialise the external ports

-- Reset test chip model. Reset period is two machine cycles long.
reset_gen: process 
begin
--    RST <= '1' ,'0' after tick * 48;
--   RST <= '0';
--   wait for tick;
   P0      <= "ZZZZZZZZ"; 
   P1      <= "ZZZZZZZZ";
   P2      <= "ZZZZZZZZ";
   P3      <= "ZZZZZZZZ";  
   NEA     <= '1';
   RST <= '1';
   wait for tick * 48;
   RST <= '0';
   wait;
end process reset_gen;

--**********************************************************************
-- Clock oscillator model
clk_cycle : process  -- free running clock
begin
   NXTAL1  <= '0';
   wait for tick;
   NXTAL1  <= '1';
   wait for tick;
end process clk_cycle;
--**********************************************************************
-- Clock gating for power down modes
gate_clocks:process(NXTAL1, IDLE, XOFF)
begin
   NX1 <= NXTAL1 or XOFF;
   NX2 <= NXTAL1 or XOFF or IDLE;
end process gate_clocks;
--**********************************************************************
-- External data memory address latch
address_latch:process(ALE, P0)
begin
   if ALE = '1' then
      EXT_ADDR(7 downto 0) <= P0;
   end if;
   EXT_ADDR(15 downto 8) <= P2;
end process address_latch;
--**********************************************************************
-- External Special Function Register Address Decoder
ext_sfr_decoder: process(FA)
begin
   if (FA = ESFR_ADDR) then
      NESFR <= '0';
   else
      NESFR <= '1';
   end if;
end process ext_sfr_decoder; 
--**********************************************************************
-- External Special Function Register
ext_sfr: process(NX2)
begin
   if NX2'event and NX2 = '1' then
      if (NESFR or NSFRWE) = '0' then
         ESFR <= FO;
      end if;
   end if;
end process ext_sfr;
--**********************************************************************
-- External Special Function Register Data Multiplexer
ext_sfr_mux: process(NSFROE, ESFR, RAM_DATA)
begin
   if NSFROE = '1' then
      -- default condition
      FI_INPUT <= RAM_DATA;
   else
      FI_INPUT <= ESFR;
   end if;
end process ext_sfr_mux; 
--**********************************************************************
-- Download Mode stimuli
dlm_stimuli: process
begin
   ale   <= 'Z';
   psen  <= 'Z';
   P0    <= "ZZZZZZZZ";
   P3(7) <= 'Z';
   P3(6) <= 'Z';
   -- allow program counter to reset
   wait for 8 * tick;
   -- enter download mode
   ale  <= '0';
   psen <= '0';
   wait for 4 * tick;
   -- set up dummy write data
   P0   <= "10101011";
   wait for 2 * tick;
   -- assert DLM write strobe
   P3(6) <= '0';
   wait for 6 * tick;
   P3(6) <= 'Z';
   wait for 2 * tick;
   -- release port 0
   P0   <= "ZZZZZZZZ";
   wait for 4 * tick;
   -- assert DLM read strobe
   P3(7) <= '0';
   wait for 6 * tick;
   P3(7) <= 'Z';
   -- wait to see program counter increment
   wait for 10 * tick;
   -- exit download mode
   ale  <= 'Z';
   psen <= 'Z';
   -- this process remains inactive for the remainder of the simulation
   wait; 
end process dlm_stimuli;
--**********************************************************************
serial_loopback: process(P3)
-- loop serial interface transmit pin to serial interface receive input
-- under control of port P3.7
begin
   if P3(7) = '0' then
     P3(0) <= P3(1);
   else
     P3(0) <= 'Z';
   end if;
end process serial_loopback;

--Test bench vector file handling
--**********************************************************************
strobeout : process
variable line_count:integer:= 0; 
variable BIRFAULT,UNIFAULT:bit := '0';
variable BIRSTATUS,UNISTATUS:bit := '0';
variable BIRCHARSREF:string(23 downto 1);
variable UNICHARSREF:string(92 downto 1);
begin
birtitle_out;
unititle_out;
birtitle_in;
unititle_in;
vector <= 0;
while (true) LOOP
        line_count := line_count + 1;
        if line_count = 40 then
           birtitle_out;
           unititle_out;
           birtitle_in;
           unititle_in;
           line_count := 0;
        end if;
--wait for = 90% of half cycle		
	wait for point9;
        VECTOR <= VECTOR +1;
        birdata_out(BIRCHARS);
        unidata_out(UNICHARS);
        birdata_in(BIRCHARSREF);
        unidata_in(UNICHARSREF);
        BIRTEMPREFCHARS <= BIRCHARSREF;
        UNITEMPREFCHARS <= UNICHARSREF;
        checkok(BIRCHARS,BIRCHARSREF,BIRFAULT);
        checkok(UNICHARS,UNICHARSREF,UNIFAULT);
        BIRFAULTFLAG <= BIRFAULT;
        UNIFAULTFLAG <= UNIFAULT;
        BIRSTATUS := BIRSTATUS or BIRFAULTFLAG;
        UNISTATUS := UNISTATUS or UNIFAULTFLAG;
        report_status(BIRSTATUS,UNISTATUS);
--wait for = half a cycle
	wait for tick;
        VECTOR <= VECTOR +1;        
        birdata_out(BIRCHARS);
        unidata_out(UNICHARS);
        birdata_in(BIRCHARSREF);
        unidata_in(UNICHARSREF);
        UNITEMPREFCHARS <= UNICHARSREF;
        BIRTEMPREFCHARS <= BIRCHARSREF;
        checkok(BIRCHARS,BIRCHARSREF,BIRFAULT);
        checkok(UNICHARS,UNICHARSREF,UNIFAULT);
        BIRFAULTFLAG <= BIRFAULT;
        UNIFAULTFLAG <= UNIFAULT;
        BIRSTATUS := BIRSTATUS or  BIRFAULTFLAG;
        UNISTATUS := UNISTATUS or  UNIFAULTFLAG;
        report_status(BIRSTATUS,UNISTATUS);
--wait for = 10% of half cycle	
	wait for point1;
end loop;
wait;
end process strobeout;

--**********************************************************************
-- Supporting functions etc to write output file
--**********************************************************************
unifault:process(VECTOR)
begin
   if UNIFAULTFLAG = '1' then
      unireportfault(UNICHARS,UNITEMPREFCHARS); 
   end if;
end process unifault;      
--**********************************************************************
birfault:process(VECTOR)
begin
   if BIRFAULTFLAG = '1' then
      birreportfault(BIRCHARS,BIRTEMPREFCHARS);
   end if;
end process birfault;      
--**********************************************************************
updatedataout:process(P0, P1, P2, P3, RST, NEA, NXTAL1, ALE, PSEN,
                      NX1, NX2, AI, BI, CI, DI, FI, ALEI, PSEI, MD, FI,
                      OA, OB, OC, OD, AE, BE, CE, DE, ALEO, NPSEN,
                      NALEN, XOFF, IDLE, M, NMOE, NMWE, DLM, FA, FO,
                      NFOE, NFWE, NSFROE, NSFRWE, NESFR)
begin
BIRCHARS <= " "&eightbit(P0(7 downto 0))&" "&eightbit(P1(7 downto 0))&
            " "&eightbit(P2(7 downto 0))&" "&eightbit(P3(7 downto 0))&
            " "&convertlogicbit(RST)&" "&convertlogicbit(NEA)&
            " "&convertlogicbit(NXTAL1)&" "&convertlogicbit(ALE)&
            " "&convertlogicbit(PSEN)&" ";

UNICHARS <=    convertlogicbit(NEA)&" "&convertlogicbit(NX1)&
            " "&convertlogicbit(NX2)&" "&convertlogicbit(RST)&
            " "&convertlogicbit(ALEI)&" "&convertlogicbit(PSEI)&
            " "&eightbit(AI(7 downto 0))&" "&eightbit(BI(7 downto 0))&
            " "&eightbit(CI(7 downto 0))&" "&eightbit(DI(7 downto 0))&
            " "&eightbit(MD(7 downto 0))&" "&eightbit(FI(7 downto 0))&
            " "&convertlogicbit(NESFR)&" "&
            " "&eightbit(OA(7 downto 0))&" "&eightbit(OB(7 downto 0))&
            " "&eightbit(OC(7 downto 0))&" "&eightbit(OD(7 downto 0))&
            " "&eightbit(AE(7 downto 0))&" "&eightbit(BE(7 downto 0))&
            " "&eightbit(CE(7 downto 0))&" "&eightbit(DE(7 downto 0))&
            " "&convertlogicbit(ALEO)&" "&convertlogicbit(NPSEN)&
            " "&convertlogicbit(NALEN)&" "&convertlogicbit(XOFF)&
            " "&convertlogicbit(IDLE)&" "&sixteenbit(M(15 downto 0))&
            " "&convertlogicbit(NMOE)&" "&convertlogicbit(NMWE)&
            " "&convertlogicbit(DLM)&" "&eightbit(FA(7 downto 0))&
            " "&eightbit(FO(7 downto 0))&
            " "&convertlogicbit(NFOE)&" "&convertlogicbit(NFWE)&
            " "&convertlogicbit(NSFROE)&" "&convertlogicbit(NSFRWE)&
            " ";
end process updatedataout;
--**********************************************************************
end m8051_tb_RTL;
--**********************************************************************