m8051_tb.vhd

another 8051 core porocesssor vhdl source code

--*******************************************************************       --
--IMPORTANT NOTICE                                                          --
--================                                                          --
--Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  --
--This file and associated deliverables are the trade secrets,              --
--confidential information and copyrighted works of Mentor Graphics         --
--Corporation and its licensors and are subject to your license agreement   --
--with Mentor Graphics Corporation.                                         --
--                                                                          --
--Use of these deliverables for the purpose of making silicon from an IC    --
--design is limited to the terms and conditions of your license agreement   --
--with Mentor Graphics If you have further questions please contact Mentor  --
--Graphics Customer Support.                                                --
--                                                                          --
--This Mentor Graphics core (m8051 v1999.120) was extracted on              --
--workstation hostid _hostid_ Inventra                                      --
--Demonstration test bench for M8051 MegaMacro
--(c) Copyright Mentor Graphics Corporation and Licensors 1998.  All Rights Reserved.
--2.001
--*********************************************************************
-- %W%  %G%   SCCS Version Control --

-- File	      :   m8051_tb.vhd
-- Library    :   WORK	
-- Created on :   May 22nd 1995
-- Purpose    :   TEST BENCH
-- Version    :   2.001
-- Mod_Date   :   6th July 1998
-- Mod_Hist   :   2.001 Serial loop back controlled by P3.7
--                2.000 Revised MegaMacro Interface, download mode
--                      demonstrated, external RAM and external SFR
--                      models included, serial interface loopback added
--                      Listing file formats revised.
--                      Internal memory inputs buffered to eliminate Zs.
--                      ALEI & PSEI contention fixed.
--                      Simulator reset mismatches confined to vector 0.
--
-- Mod_Hist  :  2.001 Revised test bench name
--
--*********************************************************************
-- Hierarchy record :
-- called by            :   none
-- calls to:
-- m8051.vhd            :       M8051 MegaMacro
-- tbs_dec              :       supporting function calls etc
-- ram.vhd              :       RAM model
-- rom.vhd              :       ROM model
-- io_buffer            :       Tristate buffers models        
--*********************************************************************
Library IEEE;
Use IEEE.std_logic_1164.all;
Use std.textio.all;

Library WORK;
Use WORK.tbs_dec.all;  
Use WORK.all;
Use WORK.SPEED.all;
--*********************************************************************
entity m8051_tb_e is
--*******************************************************************       --
--IMPORTANT NOTICE                                                          --
--================                                                          --
--Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  --
--This file and associated deliverables are the trade secrets,              --
--confidential information and copyrighted works of Mentor Graphics         --
--Corporation and its licensors and are subject to your license agreement   --
--with Mentor Graphics Corporation.                                         --
--                                                                          --
--Use of these deliverables for the purpose of making silicon from an IC    --
--design is limited to the terms and conditions of your license agreement   --
--with Mentor Graphics If you have further questions please contact Mentor  --
--Graphics Customer Support.                                                --
--                                                                          --
--This Mentor Graphics core (m8051 v1999.120) was extracted on              --
--workstation hostid _hostid_ Inventra                                      --
end m8051_tb_e ;
--*********************************************************************
architecture m8051_tb_RTL of m8051_tb_e is

-- External signal declarations
signal P0, P1, P2, P3                 : std_logic_vector(7 downto 0); 
signal RST, NEA, NXTAL1, ALE, PSEN    : std_logic;

-- Internal signal declarations
signal AI, BI, CI, DI, OA, OB, OC, OD : std_logic_vector(7 downto 0);
signal AE, BE, CE, DE                 : std_logic_vector(7 downto 0);
signal MD, FO, FI, FA                 : std_logic_vector(7 downto 0);
signal ESFR, RAM_DATA                 : std_logic_vector(7 downto 0);
signal FI_INPUT, MD_INPUT             : std_logic_vector(7 downto 0);
signal M, EXT_ADDR                    : std_logic_vector(15 downto 0);
signal ALEI, PSEI, ALEO, NPSEN, NALEN : std_logic;
signal NX1, NX2, IDLE, XOFF, DLM      : std_logic;
signal NFOE, NFWE, NMOE, NMWE, NSFROE, NSFRWE, NESFR: std_logic;
signal unused0, unused1: std_logic;
 
--text handling
signal BIRFAULTFLAG, UNIFAULTFLAG: bit;
signal BIRCHARS, BIRTEMPREFCHARS: string(23 downto 1);
signal UNICHARS, UNITEMPREFCHARS: string(92 downto 1);
signal vector:integer;

-- tick defined in speed.vhd
constant point9 : time := tick * 0.9;
constant point1 : time := tick * 0.1;

-- select an arbitrary address (E8h) for an example external SFR.
constant ESFR_ADDR : std_logic_vector(7 downto 0) := "11101000";

--*********************************************************************
component m8051 
    port(
            NMOE,
            NMWE,
            DLM,
            ALE,
            NPSEN,
            NALEN,
            NFWE,
            NFOE,
            NSFRWE,
            NSFROE,
            IDLE,
            XOFF:
            out std_logic;
            OA,
            OB,
            OC,
            OD,
            AE,
            BE,
            CE,
            DE,
            FA,
            FO:
            out std_logic_vector(7 downto 0);
            M:
            out std_logic_vector(15 downto 0);
            NX1,
            NX2,
            RST,
            NEA,
            NESFR,
            ALEI,
            PSEI:
            in std_logic;
            AI,
            BI,
            CI,
            DI,
            FI,
            MD:
            in std_logic_vector(7 downto 0)
            );
end component;
--*********************************************************************
component rom 
-- Size 4Kx8
   port (OUT_DATA    : inout std_logic_vector(7 downto 0);
         Address     : in std_logic_vector(11 downto 0);
         NROMRD, NCS : in std_logic
         );
end component;
--*********************************************************************
component ram
   port (DATA_OUT: out std_logic_vector(7 downto 0);
         DATA_IN : in std_logic_vector(7 downto 0);
         Address : in std_logic_vector(7 downto 0);
         NRAWR,
         NRARD,
         NCS     : in std_logic
         );
end component;
--*********************************************************************
component io_buffer
   port (P0_I,
         P1_I,
         P2_I,
         P3_I,
         BUFF_FI,
         BUFF_MD
         :out std_logic_vector(7 downto 0);
         ALEI, PSEI: out std_logic;
         P0_OI,
         P1_OI,
         P2_OI,
         P3_OI,
         P0_C,
         P1_C,
         P2_C,
         P3_C,
         FI_INPUT,
         MD_INPUT
         :in std_logic_vector(7 downto 0);
         ALEO, NPSEN, NALEN: in std_logic;
         P0,
         P1,
         P2,
         P3:
         inout std_logic_vector(7 downto 0);
         ALE, PSEN: inout std_logic
         );
end component;
--*********************************************************************
begin
U1:io_buffer
port map(
   P0_I(7 downto 0) => AI(7 downto 0),
   P1_I(7 downto 0) => BI(7 downto 0),
   P2_I(7 downto 0) => CI(7 downto 0),
   P3_I(7 downto 0) => DI(7 downto 0),
   ALEI => ALEI,
   PSEI => PSEI,
   P0_OI(7 downto 0) => OA(7 downto 0),
   P1_OI(7 downto 0) => OB(7 downto 0),
   P2_OI(7 downto 0) => OC(7 downto 0),
   P3_OI(7 downto 0) => OD(7 downto 0),
   ALEO => ALEO,
   NPSEN => NPSEN,
   P0_C(7 downto 0) => AE(7 downto 0),
   P1_C(7 downto 0) => BE(7 downto 0),
   P2_C(7 downto 0) => CE(7 downto 0),
   P3_C(7 downto 0) => DE(7 downto 0),
   NALEN => NALEN,
   P0(7 downto 0) => P0(7 downto 0),
   P1(7 downto 0) => P1(7 downto 0),
   P2(7 downto 0) => P2(7 downto 0),
   P3(7 downto 0) => P3(7 downto 0),
   ALE => ALE,
   PSEN => PSEN,
   BUFF_FI => FI,
   FI_INPUT => FI_INPUT,
   BUFF_MD => MD,
   MD_INPUT => MD_INPUT
   );
--*********************************************************************
U2:m8051
port map(
   AE => AE,
   BE => BE,
   CE => CE,
   DE => DE,

   FA => FA,
   FO => FO,
   M  => M,

   OA => OA,
   OB => OB,
   OC => OC,
   OD => OD,

   AI => AI,
   BI => BI,
   CI => CI,
   DI => DI,

   FI => FI,
   MD => MD,

   ALE => ALEO,
   DLM => DLM,
   NALEN => NALEN,
   NFOE => NFOE,
   NFWE => NFWE,
   NSFRWE => NSFRWE,
   NSFROE => NSFROE,
   NMOE => NMOE,
   NMWE => NMWE,
   NPSEN => NPSEN,
   IDLE => IDLE,
   XOFF => XOFF,
   ALEI => ALEI,
   NEA => NEA,
   NESFR => NESFR,
   NX1 => NX1,
   NX2 => NX2,
   PSEI => PSEI,
   RST =>RST