m8051.vhd

another 8051 core porocesssor vhdl source code

--*******************************************************************       --
--IMPORTANT NOTICE                                                          --
--================                                                          --
--Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  --
--This file and associated deliverables are the trade secrets,              --
--confidential information and copyrighted works of Mentor Graphics         --
--Corporation and its licensors and are subject to your license agreement   --
--with Mentor Graphics Corporation.                                         --
--                                                                          --
--Use of these deliverables for the purpose of making silicon from an IC    --
--design is limited to the terms and conditions of your license agreement   --
--with Mentor Graphics If you have further questions please contact Mentor  --
--Graphics Customer Support.                                                --
--                                                                          --
--This Mentor Graphics core (m8051 v1999.120) was extracted on              --
--workstation hostid _hostid_ Inventra                                      --

library IEEE;
library vhd_lib;

use IEEE.std_logic_1164.all;
use vhd_lib.all;

package CONV_PACK_m8051 is
--*******************************************************************       --
--IMPORTANT NOTICE                                                          --
--================                                                          --
--Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  --
--This file and associated deliverables are the trade secrets,              --
--confidential information and copyrighted works of Mentor Graphics         --
--Corporation and its licensors and are subject to your license agreement   --
--with Mentor Graphics Corporation.                                         --
--                                                                          --
--Use of these deliverables for the purpose of making silicon from an IC    --
--design is limited to the terms and conditions of your license agreement   --
--with Mentor Graphics If you have further questions please contact Mentor  --
--Graphics Customer Support.                                                --
--                                                                          --
--This Mentor Graphics core (m8051 v1999.120) was extracted on              --
--workstation hostid _hostid_ Inventra                                      --

-- define attributes
attribute ENUM_ENCODING : STRING;

end CONV_PACK_m8051;

library IEEE;
library vhd_lib;

use IEEE.std_logic_1164.all;
use vhd_lib.all;

use work.CONV_PACK_m8051.all;

entity m8051 is
--*******************************************************************       --
--IMPORTANT NOTICE                                                          --
--================                                                          --
--Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  --
--This file and associated deliverables are the trade secrets,              --
--confidential information and copyrighted works of Mentor Graphics         --
--Corporation and its licensors and are subject to your license agreement   --
--with Mentor Graphics Corporation.                                         --
--                                                                          --
--Use of these deliverables for the purpose of making silicon from an IC    --
--design is limited to the terms and conditions of your license agreement   --
--with Mentor Graphics If you have further questions please contact Mentor  --
--Graphics Customer Support.                                                --
--                                                                          --
--This Mentor Graphics core (m8051 v1999.120) was extracted on              --
--workstation hostid _hostid_ Inventra                                      --

   port( NMOE, NMWE, DLM, ALE, NPSEN, NALEN, NFWE, NFOE, NSFRWE, NSFROE, IDLE, 
         XOFF : out std_logic;  OA, OB, OC, OD, AE, BE, CE, DE, FA, FO : out 
         std_logic_vector (7 downto 0);  M : out std_logic_vector (15 downto 0)
         ;  NX1, NX2, RST, NEA, NESFR, ALEI, PSEI : in std_logic;  AI, BI, CI, 
         DI, FI, MD : in std_logic_vector (7 downto 0));

end m8051;

architecture GATE of m8051 is

   component m3s003bo
      port( ALUDAT, CPRDDM : out std_logic_vector (7 downto 0);  CO, ACO, OV, 
            BBIT : out std_logic;  ACLDAT : in std_logic_vector (9 downto 0);  
            TMPDAT : in std_logic_vector (7 downto 0);  ALUC : in 
            std_logic_vector (17 downto 0);  ACCDAT : in std_logic_vector (7 
            downto 7);  BIT_POSN : in std_logic_vector (2 downto 0);  NMULAB, 
            NDIVAB, DAA, ACC0 : in std_logic);
   end component;
   
   component m3s004bo
      port( ACCADD : out std_logic_vector (9 downto 0);  PCADD : out 
            std_logic_vector (12 downto 1);  REGADD : out std_logic_vector (10 
            downto 0);  MOVX : out std_logic_vector (4 downto 0);  ALUC : out 
            std_logic_vector (17 downto 0);  CODAT, PSWC : out std_logic_vector
            (2 downto 0);  TMPADD, SPC : out std_logic_vector (3 downto 0);  
            ADDR_11BIT, JMPADPTR, LOGDI, GOCYC2, MULDIV, NMULAB, NDIVAB, DAA, 
            CJNE, RETI, EITHER_RET, RMW, JBC, IMMB3, IMMB4 : out std_logic;  
            OPC : in std_logic_vector (7 downto 0);  DAAL, DAAH : in std_logic
            );
   end component;
   
   component m3s005bo
      port( ACCDAT, BREG : out std_logic_vector (7 downto 0);  ACLDAT : out 
            std_logic_vector (9 downto 0);  PAR, ACC0, DAAL, DAAH : out 
            std_logic;  CYC : in std_logic_vector (1 downto 1);  PSWDAT : in 
            std_logic_vector (7 downto 6);  STATD : in std_logic_vector (6 
            downto 2);  ACCADD : in std_logic_vector (9 downto 0);  ALUDAT, 
            CPRDDM, RDAT, IMMDAT, RAMDI : in std_logic_vector (7 downto 0);  
            SFRW : in std_logic_vector (21 downto 20);  DAA, LCYC, DIV2CK, CO, 
            RST, NX1 : in std_logic);
   end component;
   
   component m3s006bo
      port( TMPDAT : out std_logic_vector (7 downto 0);  PROGRAM_COUNT : in 
            std_logic_vector (15 downto 0);  RDAT, IMMDAT, DPH, DPL, BREG : in 
            std_logic_vector (7 downto 0);  TMPADD : in std_logic_vector (3 
            downto 0);  CODAT : in std_logic_vector (2 downto 0);  CYC : in 
            std_logic_vector (1 downto 1);  STATD : in std_logic_vector (5 
            downto 2);  LOGDI, DIV2CK, NX1, RST : in std_logic);
   end component;
   
   component m3s007bo
      port( C_TRUE : out std_logic;  ALUDAT : in std_logic_vector (7 downto 0);
            OPC : in std_logic_vector (7 downto 4);  PSWDAT : in 
            std_logic_vector (7 downto 7);  CYC : in std_logic_vector (2 downto
            2);  STATD : in std_logic_vector (3 downto 3);  BBIT, DIV2CK, NX1, 
            RST : in std_logic);
   end component;
   
   component m3s008bo
      port( WEP, NFOE, NFWE, NSFROE, NSFRWE : out std_logic;  BIT_POSN : out 
            std_logic_vector (2 downto 0);  RAMDI, FA, RDAT : out 
            std_logic_vector (7 downto 0);  SFRW : out std_logic_vector (21 
            downto 0);  JBC, EITHER_RET, C_TRUE, NESFR, CLEAR, LCYC, RESINT, 
            DIV2CK, NX1, RST : in std_logic;  ALUDAT, IMMDAT, SFRDAT, SP, IROMD
            , FI : in std_logic_vector (7 downto 0);  CYC : in std_logic_vector
            (2 downto 1);  OPC : in std_logic_vector (3 downto 0);  PSWDAT : in
            std_logic_vector (4 downto 3);  REGADD : in std_logic_vector (10 
            downto 0);  STATD : in std_logic_vector (6 downto 1);  STACK_DATA :
            in std_logic_vector (15 downto 0));
   end component;
   
   component m3s010bo
      port( EXT_PROG_EN, EXT_ROM : out std_logic;  DPL, DPH : out 
            std_logic_vector (7 downto 0);  STACK_DATA, PROGRAM_COUNT, 
            PROGRAM_ADDR : out std_logic_vector (15 downto 0);  NEA, LCYC, DLM,
            DLMSTB, INTA, IDLE, C_TRUE, ADDR_11BIT, JMPADPTR, CLEAR, DIV2CK, 
            NX1 : in std_logic;  VECTOR_ADDR : in std_logic_vector (4 downto 1)
            ;  RDAT, ALUDAT, IMMDAT, RAMDI, MSIZ : in std_logic_vector (7 
            downto 0);  CYC : in std_logic_vector (2 downto 1);  OPC : in 
            std_logic_vector (7 downto 5);  PCADD : in std_logic_vector (12 
            downto 1);  STATD : in std_logic_vector (6 downto 1);  SFRW : in 
            std_logic_vector (15 downto 14));
   end component;
   
   component m3s015bo
      port( LOV1 : out std_logic;  TCON, TMOD, TLA, TLB, THA, THB : out 
            std_logic_vector (7 downto 0);  IACK : in std_logic_vector (3 
            downto 0);  DI : in std_logic_vector (5 downto 2);  STATD : in 
            std_logic_vector (6 downto 6);  RAMDI : in std_logic_vector (7 
            downto 0);  SFRW : in std_logic_vector (9 downto 4);  RMW, S_EN, 
            T_EN, STATE12, DIV2CK1, NX1, NX2, CLEAR : in std_logic);
   end component;
   
   component m3s018bo
      port( ALE, NPSEN, MOEI, EXPMEM : out std_logic;  OAI, OB, OC, OD, AE, BE,
            CE, DE, PORTA, PORTB, PORTC, PORTD : out std_logic_vector (7 downto
            0);  PROGRAM_ADDR : in std_logic_vector (15 downto 0);  AI, BI, CI,
            DI, RAMDI, DPL, DPH, ACCDAT, FA : in std_logic_vector (7 downto 0);
            STATD : in std_logic_vector (6 downto 1);  MOVX : in 
            std_logic_vector (4 downto 0);  SFRW : in std_logic_vector (3 
            downto 0);  CYC : in std_logic_vector (2 downto 1);  PCON : in 
            std_logic_vector (0 downto 0);  XROM, EXT_PROG_EN, NEA, RXDO, TXDO,
            RMW, DIV2CK, NX1, NX2, CLEAR, RST, DLMR : in std_logic);
   end component;
   
   component m3s019bo
      port( INTA : out std_logic;  IE, IP : out std_logic_vector (7 downto 0); 
            VECTOR_ADDR : out std_logic_vector (4 downto 1);  IACK : out 
            std_logic_vector (3 downto 0);  RITI, WEP, RETI, LCYC, T_EN, S_EN, 
            DIV2CK, CLEAR, RST, NX1, NX2 : in std_logic;  STATD : in 
            std_logic_vector (1 downto 1);  CYC : in std_logic_vector (2 downto
            2);  TCON : in std_logic_vector (7 downto 1);  RAMDI : in 
            std_logic_vector (7 downto 0);  SFRW : in std_logic_vector (13 
            downto 12));
   end component;
   
   component m3s020bo
      port( RESINT : out std_logic;  SP, PCON, PSWDAT, MSIZ : out 
            std_logic_vector (7 downto 0);  CO, ACO, OV, PAR, DAA, CJNE, OPLOAD
            , MULDIV, INTA, LCYC, DIV2CK2, CLEAR, RST, STATE12, NX1, NX2 : in 
            std_logic;  CYC : in std_logic_vector (2 downto 1);  PSWC : in 
            std_logic_vector (2 downto 0);  SPC : in std_logic_vector (3 downto
            0);  STATD : in std_logic_vector (6 downto 1);  RAMDI : in 
            std_logic_vector (7 downto 0);  SFRW : in std_logic_vector (19 
            downto 16));