hier_compile.scr

another 8051 core porocesssor vhdl source code

/* Synthesis script for M8051 Soft Core interface (VHDL)                      */
/* Copyright Mentor Graphics Corporation and Licensors 1999.                  */
/* V2.000
/******************************************************************************/
/* File         :       %M%                                                   */
/* Created on   :                                                             */
/* Purpose      :       This Synopsys dc_shell script compiles the M8051      */
/* Version      :       2.000                                                 */
/* Mod Date     :       %G%                                                   */
/* Mod History  :       Cell references are from UMC 0.18um library           */
/*                      Simplified compile strategy                           */
/*                                                                            */
/******************************************************************************/

compile_preserve_sync_resets="true"

/* Echo start time */
sh date

/* Don't use jk flip-flops */
   set_dont_use umc18_slow/JKFF*

/* Don't use scan flip-flops */
   set_dont_use umc18_slow/DFFQS*
   set_dont_use umc18_slow/DFFS*

/* Don't use flip-flop with tristate output */
   set_dont_use umc18_slow/DFF_RB_OE*

/* READ VHDL SOURCE FILES */
read -format vhdl ../../rtl/m3s001bo.vhd
read -format vhdl ../../rtl/m3s002bo.vhd
read -format vhdl ../../rtl/m3s005bo.vhd
read -format vhdl ../../rtl/m3s006bo.vhd
read -format vhdl ../../rtl/m3s007bo.vhd
read -format vhdl ../../rtl/m3s009bo.vhd
read -format vhdl ../../rtl/m3s013bo.vhd
read -format vhdl ../../rtl/m3s014bo.vhd
read -format vhdl ../../rtl/m3s018bo.vhd
read -format vhdl ../../rtl/m3s019bo.vhd
read -format vhdl ../../rtl/m3s022bo.vhd
read -format vhdl ../../rtl/m3s023bo.vhd
read -format vhdl ../../rtl/m3s024bo.vhd
read -format vhdl ../../rtl/m3s025bo.vhd
read -format vhdl ../../rtl/m3s027bo.vhd
read -format vhdl ../../rtl/m3s029bo.vhd
read -format vhdl ../../rtl/m3s030bo.vhd
read -format vhdl ../../rtl/m3s031bo.vhd
read -format vhdl ../../rtl/m3s032bo.vhd
read -format vhdl ../../rtl/m3s033bo.vhd
read -format vhdl ../../rtl/m3s034bo.vhd
read -format vhdl ../../rtl/m3s035bo.vhd
read -format vhdl ../../rtl/m3s039bo.vhd
read -format vhdl ../../rtl/m3s040bo.vhd
read -format vhdl ../../rtl/m3s041bo.vhd
read -format vhdl ../../rtl/m3s003bo.vhd
read -format vhdl ../../rtl/m3s004bo.vhd
read -format vhdl ../../rtl/m3s008bo.vhd
read -format vhdl ../../rtl/m3s011bo.vhd
read -format vhdl ../../rtl/m3s016bo.vhd
read -format vhdl ../../rtl/m3s020bo.vhd
read -format vhdl ../../rtl/m3s028bo.vhd
read -format vhdl ../../rtl/m3s010bo.vhd
read -format vhdl ../../rtl/m3s015bo.vhd
read -format vhdl ../../rtl/m8051.vhd

/* Ungroup Primitive Elements */

set_ungroup m3s002bo       /* 1-bit ALU element */
set_ungroup m3s041bo       /* 4-bit ALU carry look ahead element */
set_ungroup m3s022bo       /* Opcode Decode sub-block */
set_ungroup m3s024bo       /* Opcode Decode sub-block */
set_ungroup m3s032bo       /* Opcode Decode sub-block */
set_ungroup m3s033bo       /* Opcode Decode sub-block */
set_ungroup m3s034bo       /* Opcode Decode sub-block */
set_ungroup m3s035bo       /* Opcode Decode sub-block */
set_ungroup m3s027bo       /* 4-bit sum slice of program counter */
set_ungroup m3s040bo       /* 4-bit carry slice of program counter */
set_ungroup m3s029bo       /* UART 1-bit counter element */
set_ungroup m3s030bo       /* UART Tx Shift register */
set_ungroup m3s031bo       /* UART Rx Shift register */

/* Uniquify multiple instantiations */
current_design "m8051"
uniquify

/* Apply Constraints for the first pass compilation */

current_design "m8051"
/* Set interface delays and clock periods */
include hier_setup.scr

/* Declare multicycle and false paths */
include m8051_exp.mcp 
include m8051_exp.sfp 

/* Top down hierarchical compilation */
current_design m8051
compile -map_effort medium

/************************************************************************/
/*	Write the synthesis results					*/
/************************************************************************/

vhdlout_single_bit = user
vhdlout_equations = false
vhdlout_use_packages = vhdlout_use_packages + {vhd_lib.Vcomponents}
vhdlout_write_components = true
vhdlout_architecture_name = GATE
vhdlout_preserve_hierarchical_types = user


/* Write out db */
write -hierarchy -f db -output m8051.db

/* Change names and output design, timings, violations, etc */
change_names -rules vhdl -hierarchy > chg_name.rpt

/* write out VHDL netlist */

write -hierarchy -format vhdl -output m8051.vhd.tmp
sh sed -e "s+vhd_lib.Vcomponents.all+vhd_lib.all+g" m8051.vhd.tmp > ../../gates/synop/m8051.vhd

write_timing -f sdf-v2.1 -o m8051.sdf.tmp
sh perl sdf.pl m8051.sdf.tmp vhdl > ../../gates/synop/m8051.sdf

/************************************************************************/
/*      Generate reports                                                */
/************************************************************************/

/* Report Coding Issues */
check_design > chk_des.rpt

report_design >  m8051warp.rpt

report_constraints -verbose > constraint.rpt
report_constraints -all_violators > violation_all.rpt
report_constraints -all_violators -verbose > violation_verb.rpt

report_area >  area.rpt
check_timing

report_timing -path full -delay max -max_paths 5 -nworst 5 > timing.rpt

/*  FINISH TIME */
sh date

quit