m3s035bo.vhd

来自「another 8051 core porocesssor vhdl sourc」· VHDL 代码 · 共 195 行

--*******************************************************************       --
--IMPORTANT NOTICE                                                          --
--================                                                          --
--Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  --
--This file and associated deliverables are the trade secrets,              --
--confidential information and copyrighted works of Mentor Graphics         --
--Corporation and its licensors and are subject to your license agreement   --
--with Mentor Graphics Corporation.                                         --
--                                                                          --
--Use of these deliverables for the purpose of making silicon from an IC    --
--design is limited to the terms and conditions of your license agreement   --
--with Mentor Graphics If you have further questions please contact Mentor  --
--Graphics Customer Support.                                                --
--                                                                          --
--This Mentor Graphics core (m8051 v1999.120) was extracted on              --
--workstation hostid _hostid_ Inventra                                      --
--Register File Control Decoder for M8051
--Copyright Mentor Graphics Corporation and Licensors 1999. All rights reserved
--v1.005
--*********************************************************************
--@(#)m3s035bo.vhd	1.2 04/08/99 SCCS Version Control

--File	        :       m3s035bo.vhd
--Created on    :       4 Jan 1996
--Purpose       :       M8051 Register File Control Decoder
--Version       :       1.005
--Mod Date      :       22nd January 1999
--Mod History	:	1.005 Redundant ESFR read cycles masked out during jumps
--                            Intermediate terms removed.
--                      1.004 _e suffix removed from entity names.
--                      1.003 Comments added for REGADD(5-10)
--                      1.002 ECN 878: CTRU removed from decoder
--
--*********************************************************************
--Hierarchy record      :
--Called by             :m3s004bo.vhd
--Calls to              :None
--*********************************************************************
library IEEE;

use IEEE.std_logic_1164.all;
library WORK;

--*********************************************************************
--Entity Definition
--*********************************************************************

entity m3s035bo is 
--*******************************************************************       --
--IMPORTANT NOTICE                                                          --
--================                                                          --
--Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  --
--This file and associated deliverables are the trade secrets,              --
--confidential information and copyrighted works of Mentor Graphics         --
--Corporation and its licensors and are subject to your license agreement   --
--with Mentor Graphics Corporation.                                         --
--                                                                          --
--Use of these deliverables for the purpose of making silicon from an IC    --
--design is limited to the terms and conditions of your license agreement   --
--with Mentor Graphics If you have further questions please contact Mentor  --
--Graphics Customer Support.                                                --
--                                                                          --
--This Mentor Graphics core (m8051 v1999.120) was extracted on              --
--workstation hostid _hostid_ Inventra                                      --
       port(REGADD:
            out std_logic_vector(10 downto 0);
            NCALL,
            NPOP,
            NPUSH:
            out std_logic;
            HIDA:
            in std_logic_vector(3 downto 0);
            LODEC:
            in std_logic_vector(2 downto 0);
            OPC:
            in std_logic_vector(4 downto 3);
            HIDB:
            in std_logic_vector(8 downto 7);
            HIDC:
            in std_logic_vector(13 downto 10);
            HI15,
            L5TF,
            NLCA,
            BRET,
            INDOP,
            INDXR,
            INDXW,
            NLDA,
            LOGDI,
            NMBC,
            JBC,
            NBEN,
            NSWA,
            NMCB:
            in std_logic
            );
end m3s035bo;
--*********************************************************************
--Architecture definition
--*********************************************************************
architecture m3s035bo_rtl of m3s035bo is
--*********************************************************************
signal AA, AB, AC, AD, AE, AF, AG, AH, AI, AJ, AK, AL, AM, AO, AP: std_logic;
signal CALLRETS: std_logic;
--*********************************************************************
begin
--Notes
--Register File Mux Control (REGADD) defined as
--
--REGADD (0 to 4)
--
--      0 1 2 3 4 Function
--      --------------------
--      0 0 X X X Load Register from ALU
--      1 0 X X X Load Register from IMM
--      0 1 X X X Load Register for Nibble Swap
--      1 1 X X X Load Register from PC
--      X X 0 X X Register Address Unchanged
--      X X 1 X X Reg Address Control: cycle1 - bits 3&4, in cyc2 - 5&6.
--      X X X 0 0 Register Address Direct
--      X X X 1 0 Register Address Register Bank
--      X X X 0 1 Register Address Stack Pointer
--      X X X 1 1 Register Address Indirect
--
-- REGADD (4 to 10)
--
--      5 6 7 8 9 10   Function
--      ---------------------------------------------------------------
--      0 0 X X X X    Second Register Address Direct
--      1 0 X X X X    Second Register Address Register Bank
--      0 1 X X X X    Second Register Address Stack Pointer
--      1 1 X X X X    Second Register Address Indirect
--      X X 0 X X X    Not Register Indirect Address Enable
--      X X 1 X X X    Register Indirect Address Enable
--      X X X 0 X X    No Register Load 
--      X X X 1 X X    Register Load 
--      X X X X 0 X    No Second Register Load
--      X X X X 1 X    Second Register Load (used by CALL instructions)
--      X X X X X 0    Not Register Bit Addressing Mode
--      X X X X X 1    Register Bit Addressing Mode
--
--*********************************************************************
misc1:process(HIDA,HIDB,HIDC,HI15,JBC,L5TF,LODEC,INDOP,INDXR,INDXW,OPC,NLCA)
begin
-- Generate intermediate signal prior to producing regadd(0,1,2,3,4)
AA <= HIDB(7) and L5TF;
AB <= (LODEC(1) and OPC(4)) or not NLCA;
AC <= (HIDC(12) or HIDC(13)) and LODEC(0);
AD <= L5TF and HIDB(8);
AE <= (INDOP or OPC(3)) and HIDC(10);
AF <= OPC(3) and not HIDC(10);
AG <= HIDC(13) and LODEC(0);
AH <= (not HIDC(10) and INDOP) or INDXR or INDXW;
AI <= (LODEC(1) and not OPC(4)) or (LODEC(2) and HIDA(0));
--generate intermediate signals prior to producing regadd(5,6,7,8,9,10)
AJ <= HIDC(10) and OPC(3);
AK <= HIDC(12) and LODEC(0);
AL <= INDOP and HIDC(10);
AM <= (HIDA(0) or HIDA(1) or HIDB(7) or HIDB(8) or HIDC(10) or HIDC(12) or
       HIDC(13) or HI15) and L5TF;
AO <= (HIDC(11) or HIDC(12) or HIDC(13)) and LODEC(2);
AP <= (HIDA(2) or HIDA(3) or HIDC(10) or HIDC(11)) and LODEC(0);
end process misc1;
--*********************************************************************
regout1:process(AA, AB, AC, AD, AE, AF, AG, AH, AI, NSWA, CALLRETS)
begin
REGADD(0)  <= AA or AB;
REGADD(1)  <= not NSWA or AB; 
REGADD(2)  <= AC or AD or AE or CALLRETS;
REGADD(3)  <= AF or AH or AI;
REGADD(4)  <= AG or CALLRETS or AH or AI;
end process regout1;
--*********************************************************************
regout2:process(AB, AC, AI, AJ, AL, AK, AM, AO, AP, INDXR, INDXW, INDOP, NLDA,
                LOGDI, NMBC, NMCB, NBEN, CALLRETS, JBC)
begin
REGADD(5)  <= AI or AJ or AL;
REGADD(6)  <= AI or AK or AL or CALLRETS;
REGADD(7)  <= INDXR or INDXW or INDOP;
REGADD(8)  <= AM or AB or AC or not NLDA or LOGDI or not NMBC or JBC or AO;
REGADD(9)  <= AB;
REGADD(10) <= AP or not NBEN or not NMCB;
end process regout2;
--*********************************************************************
miscout:process(AB,AC,AG,AK,BRET)
begin
NCALL      <= not AB;
NPOP       <= not AG;
CALLRETS   <= BRET or AB;
NPUSH      <= not AK;
end process miscout;
--*********************************************************************
end m3s035bo_rtl;
--*********************************************************************