m8051.vhd

来自「another 8051 core porocesssor vhdl sourc」· VHDL 代码 · 共 1,209 行 · 第 1/3 页

         NX1 => NX2
         ); 
--*********************************************************************
U5:m3s006bo
port map(
         TMPDAT => TMPDAT,
         PROGRAM_COUNT => PROGRAM_COUNT,
         RDAT => RDAT,
         IMMDAT => IMMDAT,
         CODAT => CODAT,
         DPH => DPH,
         DPL => DPL,
         BREG => BREG,
         TMPADD => TMPADD,
         CYC => CYC(1 downto 1),
         STATD => STATD(5 downto 2),
         LOGDI => LOGDI,
         DIV2CK => DIV2CK2,
         NX1 => NX2,
         RST => RST
         );       
--*********************************************************************
U6:m3s007bo
port map(
         C_TRUE => C_TRUE,
         ALUDAT => ALUDAT,
         OPC => OPC(7 downto 4),
         PSWDAT => PSWDAT(7 downto 7),
         CYC => CYC(2 downto 2),
         STATD => STATD(3 downto 3),
         BBIT => BBIT,
         DIV2CK => DIV2CK2,
         NX1 => NX2,
         RST => RST
         );    
--*********************************************************************
U7:m3s008bo
port map(
         WEP => WEP,
         NFOE => NFOE,
         NFWE => NFWE,            
         NSFROE => NSFROE,
         NSFRWE => NSFRWE,
         RAMDI => RAMDI,
         FA => LFA,
         BIT_POSN => BIT_POSN,
         RDAT => RDAT,
         SFRW => SFRW,
         JBC => JBC,
         EITHER_RET => EITHER_RET,
         C_TRUE => C_TRUE,
         NESFR => NESFR,
         CLEAR => CLEAR,
         LCYC => LCYC,
         RESINT => RESINT,
         DIV2CK => DIV2CK2,
         NX1 => NX2,
         RST => RST,
         ALUDAT => ALUDAT,
         IMMDAT => IMMDAT,
         SFRDAT => SFRDAT,
         SP => SP,
         IROMD => IROMD,
         FI => FI,
         CYC => CYC(2 downto 1),
         OPC => OPC(3 downto 0),
         PSWDAT => PSWDAT(4 downto 3),
         REGADD => REGADD, 
         STATD => STATD(6 downto 1),
         STACK_DATA => STACK_DATA
         );
--*********************************************************************
U8:m3s010bo
port map(
         EXT_PROG_EN => EXT_PROG_EN,
         EXT_ROM => EXT_ROM,
         DPL => DPL,
         DPH => DPH,
         STACK_DATA => STACK_DATA,
         PROGRAM_COUNT => PROGRAM_COUNT,
         PROGRAM_ADDR => PROGRAM_ADDR,
         NEA => NEA,
         LCYC => LCYC,
         DLM => LDLM,
         DLMSTB => DLMSTB,
         INTA => INTA,
         IDLE => PCON(0),
         C_TRUE => C_TRUE,
         CLEAR => CLEAR,
         DIV2CK => DIV2CK2,
         NX1 => NX2,
         RDAT => RDAT,
         ALUDAT => ALUDAT,
         IMMDAT => IMMDAT,
         VECTOR_ADDR => VECTOR_ADDR,
         RAMDI => RAMDI,
         MSIZ => MSIZ,
         CYC => CYC(2 downto 1),
         OPC => OPC(7 downto 5),
         PCADD => PCADD,
         ADDR_11BIT => ADDR_11BIT,
         JMPADPTR => JMPADPTR,
         STATD => STATD(6 downto 1),
         SFRW => SFRW(15 downto 14)
         );
--*********************************************************************
U9:m3s015bo
port map(
         LOV1 => LOV1,
         TCON => TCON,
         TMOD => TMOD,
         TLA => TLA,
         TLB => TLB,
         THA => THA,
         THB => THB,
         IACK => IACK,
         DI => DI(5 downto 2),
         STATD => STATD(6 downto 6),
         RAMDI => RAMDI,
         SFRW => SFRW(9 downto 4),
         RMW => RMW,
         S_EN => S_EN,
         T_EN => T_EN,
         STATE12 => STATE12,
         DIV2CK1 => DIV2CK1,
         NX1 => NX1,
         NX2 => NX2,
         CLEAR => CLEAR
         );
--*********************************************************************
U10:m3s018bo
port map(
         ALE => ALE,
         NPSEN => NPSEN,
         MOEI => MOEI,
         EXPMEM =>EXPMEM,
         OAI => OAI,
         OB => OB,
         OC => OC,
         OD => OD,
         AE => AE,
         BE => BE,
         CE => CE,
         DE => DE,
         PORTA => PORTA,
         PORTB => PORTB,
         PORTC => PORTC,
         PORTD => PORTD,
         PROGRAM_ADDR => PROGRAM_ADDR,
         AI => AI,
         BI => BI,
         CI =>CI,
         DI => DI,
         RAMDI => RAMDI,
         DPL => DPL,
         DPH => DPH,
         ACCDAT => ACCDAT,
         FA => LFA,
         STATD => STATD(6 downto 1),
         MOVX => MOVX,
         SFRW => SFRW(3 downto 0),
         CYC => CYC(2 downto 1),
         PCON => PCON(0 downto 0),
         XROM => EXT_ROM,
         EXT_PROG_EN => EXT_PROG_EN,
         NEA => NEA,
         RXDO => RXDO,
         TXDO => TXDO,
         RMW => RMW,
         DIV2CK => DIV2CK2,
         NX1 => NX1,
         NX2 => NX2,
         CLEAR => CLEAR,
         RST => RST,
         DLMR => DLMR
         );
--*********************************************************************
U11:m3s019bo
port map(
         INTA => INTA,            
         IE => IE,
         IP => IP,
         VECTOR_ADDR => VECTOR_ADDR,
         IACK => IACK,
         RITI => RITI,
         WEP => WEP,
         RETI => RETI,
         LCYC => LCYC,
         T_EN => T_EN,
         S_EN => S_EN,
         DIV2CK => DIV2CK1,
         CLEAR => CLEAR,
         RST => RST,
         NX1 => NX1,
         NX2 => NX2,
         STATD => STATD(1 downto 1),
         CYC => CYC(2 downto 2),
         TCON => TCON(7 downto 1), 
         RAMDI => RAMDI,
         SFRW => SFRW(13 downto 12)
         );
--*********************************************************************
U12:m3s020bo
port map(
         RESINT => RESINT,           
         SP => SP,
         PCON => PCON,
         PSWDAT => PSWDAT,
         MSIZ => MSIZ,
         CO => CO,
         ACO => ACO,
         OV => OV,
         PAR => PAR,
         DAA => DAA,
         MULDIV => MULDIV,
         CJNE => CJNE,
         OPLOAD => OPLOAD,
         INTA => INTA,
         LCYC => LCYC,
         DIV2CK2 => DIV2CK2,
         CLEAR => CLEAR,
         RST => RST,
         STATE12 => STATE12,
         NX1 => NX1,
         NX2 => NX2,
         CYC => CYC(2 downto 1),
         PSWC => PSWC,
         SPC => SPC,
         STATD => STATD(6 downto 1),
         RAMDI => RAMDI,
         SFRW => SFRW(19 downto 16)
         );
--*********************************************************************
U13:m3s023bo
port map(
         SFRDAT => SFRDAT,
         FA => LFA(6 downto 0),
         PORTA => PORTA,
         PORTB => PORTB,
         PORTC => PORTC,
         PORTD => PORTD,
         SP => SP,
         DPL => DPL,
         DPH => DPH,
         PCON => PCON,
         TCON => TCON,
         TMOD => TMOD,
         TLA => TLA,
         TLB => TLB,
         THA => THA,
         THB => THB,
         SCON => SCON,
         SBUF => SBUF,
         IE => IE,
         IP => IP,
         PSWDAT => PSWDAT,
         ACCDAT => ACCDAT,
         BREG => BREG,
         MSIZ => MSIZ
         );            
--*********************************************************************
U14:m3s025bo
port map(
         OPC => OPC,
         OPLOAD => OPLOAD,
         IROMD => IROMD,
         STATD => STATD(1 downto 1),
         PCON => PCON(0 downto 0),
         CLEAR => CLEAR,
         RST => RST,
         DIV2CK => DIV2CK2,
         NX1 => NX2,
         INTA => INTA,
         LCYC => LCYC,
         DLM => LDLM
         );
--*********************************************************************
U15:m3s028bo
port map(
         SCON => SCON,
         SBUF => SBUF,
         RITI => RITI,
         RXDO => RXDO,
         TXDO => TXDO,
         DI => DI(0 downto 0),
         STATE12 => STATE12,
         RAMDI => RAMDI,
         PCON => PCON(7 downto 7),
         SFRW => SFRW(11 downto 10),
         LOV1 => LOV1,
         S_EN => S_EN,
         T_EN => T_EN,
         DIV2CK1 => DIV2CK1,
         NX1 => NX1,
         NX2 => NX2,
         CLEAR => CLEAR
         );
--*********************************************************************
-- Process Definitions
--*********************************************************************
muxoa:process(OAI, IROMD, RAMDI, AI, LDLM)
-- Download mode multiplexer for combinatorial program data read and
-- write paths.
begin
   if LDLM = '0' then
      OA <= OAI;
      FO <= RAMDI;
   else
      OA <= IROMD;
      FO <= AI;
   end if;
end process muxoa;
--*********************************************************************
misc1:process(DIV2CK2, STATD, MOVX, PCADD, IMMB4, LCYC, CYC, LDLM, DI,
              IMMB3, DLMSTQ)
-- Immediate data register write enable and download mode controls.
begin
   IMMDATEN <= DIV2CK2 and ((STATD(3) and MOVX(0))
                          or (STATD(1) and IMMB3 and not LCYC)
                          or (STATD(4) and (CYC(1) or IMMB4)) );
   DLMSTBI <= (DI(6) and DI(7)) or not LDLM;
   DLMR <= LDLM and not DI(7);
   DLMSTB <= DLMSTQ(0) and not DLMSTQ(1) and LDLM;
end process misc1;
--*********************************************************************
muxiromd:process(MD, AI, STATD, MOVX, EXPMEM)
-- Internal/external program memory multiplexer
begin
   if ((STATD(3) and MOVX(0)) or EXPMEM) ='0' then
      IROMD <= MD;
   else
      IROMD <= AI;
   end if;
end process muxiromd;
--*********************************************************************
setclear:process(NX1,RST)
-- Synchronous clear register.
begin
   if RST = '1' then
       CLEAR <= '1';
   elsif NX1'event and NX1 ='1' then
     if (S_EN and (CYC(1) or CLEAR)) = '1' then
       CLEAR <=  '0';
     end if;
   end if;
end process setclear;
--*********************************************************************
setimmdat:process(NX2)
-- Immediate program data register
begin
   if NX2'event and NX2 ='1' then
      if IMMDATEN = '1' then
         IMMDAT <= IROMD;
      end if;
   end if;
end process setimmdat;
--*********************************************************************
setdlmstq:process(NX1)
-- Download mode program counter increment strobe synchroniser
begin
if NX1'event and NX1 ='1' then
      DLMSTQ(0) <= DLMSTBI;
      DLMSTQ(1) <= DLMSTQ(0);
end if;
end process setdlmstq;
--*********************************************************************
direction_ap:process(RST)
-- Bi-direct buffer control for PSEN and ALE signals
begin
  NALEN <= RST;
end process direction_ap;
--*********************************************************************
setdlm:process(NX1)
-- Enter download mode during reset only and at least two clock edges
-- after RST goes high, in order to allow ALE and PSEN to tri-state 
-- first.
begin
if NX1'event and NX1 ='1' then
   LDLM <= RST and not PSEI and not ALEI;
end if;
end process setdlm;
--*********************************************************************
prog_mem_strobes:process(DI,LDLM,MOEI)
-- Internal program memory control outputs.
-- Write strobe (NMWE) may only be active during download mode.
begin
  NMWE <= DI(6) or not LDLM;
  NMOE <= (DI(7) or not LDLM) and (LDLM or not MOEI);
end process prog_mem_strobes;
--*********************************************************************
localout:process(LFA, LDLM, PCON, PROGRAM_ADDR)
-- Rename internal signals for export beyond MegaMacro boundary.
begin
   FA <= LFA;
   DLM <= LDLM;
   XOFF <= PCON(1);
   IDLE <= PCON(0);
   M <= PROGRAM_ADDR;
end process localout;
--*********************************************************************
end m8051_rtl;
--*********************************************************************