m8051.vhd

来自「another 8051 core porocesssor vhdl sourc」· VHDL 代码 · 共 1,209 行 · 第 1/3 页

            VECTOR_ADDR:
            in std_logic_vector(4 downto 1);            
            RDAT,
            ALUDAT,
            IMMDAT,
            RAMDI,
            MSIZ:
            in std_logic_vector(7 downto 0);
            CYC:
            in std_logic_vector(2 downto 1);
            OPC:
            in std_logic_vector(7 downto 5);
            PCADD:
            in std_logic_vector(12 downto 1);
            STATD:
            in std_logic_vector(6 downto 1);
            SFRW:
            in std_logic_vector(15 downto 14)
            );
end component;
--*********************************************************************
--Timer counter
component m3s015bo
       port(LOV1:
            out std_logic;
            TCON,
            TMOD,
            TLA,
            TLB,
            THA,
            THB:
            out std_logic_vector(7 downto 0);
            IACK:
            in std_logic_vector(3 downto 0);
            DI:
            in std_logic_vector(5 downto 2);
            STATD:
            in std_logic_vector(6 downto 6);
            RAMDI:
            in std_logic_vector(7 downto 0);
            SFRW:
            in std_logic_vector(9 downto 4);
            RMW,
            S_EN,
            T_EN,
            STATE12,
            DIV2CK1,
            NX1,
            NX2,
            CLEAR:
            in std_logic
            );
end component;
--*********************************************************************
--I/O port control
component m3s018bo
       port(ALE,
            NPSEN,
            MOEI,
            EXPMEM:
            out std_logic;
            OAI,
            OB,
            OC,
            OD,
            AE,
            BE,
            CE,
            DE,
            PORTA,
            PORTB,
            PORTC,
            PORTD:
            out std_logic_vector(7 downto 0);
            PROGRAM_ADDR:
            in std_logic_vector(15 downto 0);
            AI,
            BI,
            CI,
            DI,
            RAMDI,
            DPL,
            DPH,
            ACCDAT,
            FA:
            in std_logic_vector(7 downto 0);
            STATD:
            in std_logic_vector(6 downto 1);
            MOVX:
            in std_logic_vector(4 downto 0);
            SFRW:
            in std_logic_vector(3 downto 0);
            CYC:
            in std_logic_vector(2 downto 1);
            PCON:
            in std_logic_vector(0 downto 0);
            XROM,
            EXT_PROG_EN,
            NEA,
            RXDO,
            TXDO,
            RMW,
            DIV2CK,
            NX1,
            NX2,
            CLEAR,
            RST,
            DLMR:
            in std_logic
            );
end component;
--*********************************************************************
--Interrupt control
component m3s019bo
       port(INTA:            
            out std_logic;
            IE,
            IP:
            out std_logic_vector(7 downto 0);
            VECTOR_ADDR:
            out std_logic_vector(4 downto 1);
            IACK:
            out std_logic_vector(3 downto 0);
            RITI,
            WEP,
            RETI,
            LCYC,
            T_EN,
            S_EN,
            DIV2CK,
            CLEAR,
            RST,
            NX1,
            NX2:
            in std_logic;
            STATD:
            in std_logic_vector(1 downto 1);
            CYC:
            in std_logic_vector(2 downto 2);
            TCON: --even bits not used
            in std_logic_vector(7 downto 1);
            RAMDI:
            in std_logic_vector(7 downto 0);
            SFRW:
            in std_logic_vector(13 downto 12)
            );
end component;
--*********************************************************************
--miscellaneous special function registers
component m3s020bo
       port(RESINT:            
            out std_logic;
            SP,
            PCON,
            PSWDAT,
            MSIZ:
            out std_logic_vector(7 downto 0);
            CO,
            ACO,
            OV,
            PAR,
            DAA,
            CJNE,
            OPLOAD,
            MULDIV,
            INTA,
            LCYC,
            DIV2CK2,
            CLEAR,
            RST,
            STATE12,
            NX1,
            NX2:
            in std_logic;
            CYC:
            in std_logic_vector(2 downto 1);
            PSWC:
            in std_logic_vector(2 downto 0);
            SPC:
            in std_logic_vector(3 downto 0);
            STATD:
            in std_logic_vector(6 downto 1);
            RAMDI:
            in std_logic_vector(7 downto 0);
            SFRW:
            in std_logic_vector(19 downto 16)
            );
end component;
--*********************************************************************
--special function register output multiplexer
component m3s023bo
       port(SFRDAT:
            out std_logic_vector(7 downto 0);
            FA:
            in std_logic_vector(6 downto 0);
            PORTA,
            PORTB,
            PORTC,
            PORTD,
            SP,
            DPL,
            DPH,
            PCON,
            TCON,
            TMOD,
            TLA,
            TLB,
            THA,
            THB,
            SCON,
            SBUF,
            IE,
            IP,
            PSWDAT,
            ACCDAT,
            BREG,
            MSIZ:
            in std_logic_vector(7 downto 0)
            );       
end component;
--*********************************************************************
--Opcode Register
component m3s025bo
       port(OPC:
            out std_logic_vector(7 downto 0);
            OPLOAD:
            out std_logic;
            IROMD:
            in std_logic_vector(7 downto 0);
            STATD:
            in std_logic_vector(1 downto 1);
            PCON:
            in std_logic_vector(0 downto 0);
            CLEAR,
            RST,
            DIV2CK,
            NX1,
            INTA,
            LCYC,
            DLM:
            in std_logic
            );
end component;
--*********************************************************************
--UART
component m3s028bo
       port(SCON,
            SBUF:
            out std_logic_vector(7 downto 0);
            RITI,
            RXDO,
            TXDO:
            out std_logic;
            DI:
            in std_logic_vector(0 downto 0);
            RAMDI:
            in std_logic_vector(7 downto 0);
            PCON:
            in std_logic_vector(7 downto 7);
            SFRW:
            in std_logic_vector(11 downto 10);
            LOV1,
            S_EN,
            T_EN,
            STATE12,
            DIV2CK1,
            NX1,
            NX2,
            CLEAR:
            in std_logic
            );
end component;
--*********************************************************************
--Signal definitions
--*********************************************************************
signal DIV2CK1, DIV2CK2, CLEAR:std_logic;
signal NMULAB,NDIVAB:std_logic;
signal LCYC,GOCYC2,MULDIV,S_EN,T_EN,STATE12,LOGDI:std_logic;
signal C_TRUE,DAAL,DAAH,DAA,EXPMEM,INTA,OPLOAD,RETI,RMW,PAR:std_logic;
signal ACC0,ACO,BBIT,CO,IMMB3,IMMB4,OV,RESINT,WEP:std_logic;
signal DLMR,DLMSTB,DLMSTBI,RITI,RXDO,TXDO:std_logic;
signal LOV1,MOEI:std_logic;
signal IMMDATEN,JMPADPTR:std_logic;
signal LDLM, EXT_PROG_EN, EXT_ROM:std_logic;
signal JBC, CJNE, EITHER_RET:std_logic;
signal ADDR_11BIT:std_logic;
signal CODAT,BIT_POSN,PSWC:std_logic_vector(2 downto 0);
signal DLMSTQ: std_logic_vector(2 downto 0);
signal CYC:std_logic_vector(3 downto 1);
signal IACK,SPC,TMPADD:std_logic_vector(3 downto 0);
signal VECTOR_ADDR:std_logic_vector(4 downto 1);
signal MOVX:std_logic_vector(4 downto 0);
signal ACCDAT,ALUDAT,BREG,CPRDDM,IE,IP:std_logic_vector(7 downto 0);
signal IMMDAT,IROMD,MSIZ,OPC,DPH,DPL,OAI:std_logic_vector(7 downto 0);
signal PCON,PSWDAT,RAMDI,RDAT,SBUF,SCON:std_logic_vector(7 downto 0);
signal PORTA,PORTB,PORTC,PORTD:std_logic_vector(7 downto 0);
signal SFRDAT,SP,TCON,TLA,TLB,THA,THB,TMOD,TMPDAT:std_logic_vector(7 downto 0);
signal LFA:std_logic_vector(7 downto 0);
signal ACCADD:std_logic_vector(9 downto 0);
signal ACLDAT:std_logic_vector(9 downto 0);
signal PCADD:std_logic_vector(12 downto 1);
signal REGADD:std_logic_vector(10 downto 0);
signal STATD:std_logic_vector(6 downto 1);
signal STACK_DATA, PROGRAM_COUNT, PROGRAM_ADDR:std_logic_vector(15 downto 0);
signal ALUC:std_logic_vector(17 downto 0);
signal SFRW:std_logic_vector(21 downto 0);
--*********************************************************************
--Port Mapping
--*********************************************************************
begin
--*********************************************************************
U1:m3s001bo
port map(
         STATD => STATD,
         CYC => CYC,
         LCYC => LCYC,
         DIV2CK1 => DIV2CK1,
         DIV2CK2 => DIV2CK2,
         S_EN => S_EN,
         T_EN => T_EN,
         STATE12 => STATE12, 
         RST => RST,
         GOCYC2 => GOCYC2,
         MULDIV => MULDIV,
         PCON(0) => PCON(0),
         NX1 => NX1,
         NX2 => NX2
         );
--*********************************************************************
U2:m3s003bo
port map(
         ALUDAT => ALUDAT,
         CPRDDM => CPRDDM,
         CO => CO,
         ACO => ACO,
         OV => OV,
         BBIT => BBIT,
         ACLDAT => ACLDAT,
         TMPDAT => TMPDAT,
         ALUC => ALUC,
         ACCDAT => ACCDAT(7 downto 7),
         BIT_POSN => BIT_POSN,
         NMULAB => NMULAB,
         NDIVAB => NDIVAB,
         DAA => DAA,
         ACC0 =>ACC0
         );
--*********************************************************************
U3:m3s004bo
port map(
         ACCADD => ACCADD,
         PCADD => PCADD,
         REGADD => REGADD,
         TMPADD => TMPADD,
         MOVX => MOVX,
         ALUC => ALUC, 
         CODAT => CODAT,
         PSWC => PSWC,
         SPC => SPC,
         ADDR_11BIT => ADDR_11BIT,
         LOGDI => LOGDI,
         JMPADPTR =>JMPADPTR,
         GOCYC2 => GOCYC2,
         MULDIV => MULDIV,
         NMULAB => NMULAB,
         NDIVAB => NDIVAB,
         DAA => DAA,
         CJNE => CJNE,
         RETI => RETI,
         EITHER_RET => EITHER_RET,
         RMW => RMW,
         JBC => JBC,
         IMMB3 => IMMB3,
         IMMB4 => IMMB4,
         OPC => OPC,
         DAAL => DAAL,
         DAAH => DAAH
         );
--*********************************************************************
U4:m3s005bo
port map(
         ACCDAT => ACCDAT,
         BREG => BREG,
         ACLDAT => ACLDAT,
         PAR => PAR,
         ACC0 => ACC0,
         DAAL => DAAL,
         DAAH => DAAH,
         CYC => CYC(1 downto 1),
         PSWDAT => PSWDAT(7 downto 6),
         STATD => STATD(6 downto 2),
         ACCADD => ACCADD,
         ALUDAT => ALUDAT,
         CPRDDM => CPRDDM,
         RDAT => RDAT,
         IMMDAT => IMMDAT,
         RAMDI => RAMDI,
         SFRW => SFRW(21 downto 20),
         DAA => DAA,
         LCYC => LCYC,
         DIV2CK => DIV2CK2,
         CO => CO,
         RST => RST,