m8051.vhd

来自「another 8051 core porocesssor vhdl sourc」· VHDL 代码 · 共 1,209 行 · 第 1/3 页

--*******************************************************************       --
--IMPORTANT NOTICE                                                          --
--================                                                          --
--Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  --
--This file and associated deliverables are the trade secrets,              --
--confidential information and copyrighted works of Mentor Graphics         --
--Corporation and its licensors and are subject to your license agreement   --
--with Mentor Graphics Corporation.                                         --
--                                                                          --
--Use of these deliverables for the purpose of making silicon from an IC    --
--design is limited to the terms and conditions of your license agreement   --
--with Mentor Graphics If you have further questions please contact Mentor  --
--Graphics Customer Support.                                                --
--                                                                          --
--This Mentor Graphics core (m8051 v1999.120) was extracted on              --
--workstation hostid _hostid_ Inventra                                      --
--M8051 Megamacro Top Level
--Copyright Mentor Graphics Corporation and Licensors 1998. All rights reserved.
--Core Version 6.7 for revision history see m8051.readme
--*********************************************************************
--@(#)m8051.vhd	1.2 04/08/99 SCCS Version Control

--File	        :       m8051.vhd
--Created on    :       9th January 1996
--Purpose       :       M8051 Megamacro 
--Version       :       1.013
--Mod Date      :       2nd April 1998
--Mod History	:       1.013 _e suffix removed from entity names.
--                      1.012 Redundant signals removed, comments added.
--                      1.011 SFR Expansion Capability
--                      1.010 Name change for Verilog translation.
--                      1.009 Name changes and exports.
--                            Program counter revisions.
--                            Sensitivity list revisions.
--                            Use accumulator not ALUDAT for MOVX writes
--                      1.008 ECN 878: PCADD bus width increased, C_TRUE
--                            inserted into m3s010bo and m3s008bo.
--                            Read Modify Write affects timer counters. 
--                      1.007 LDV1 renamed LOV1
--			1.006 Idle Mode Power Saving Scheme
--			1.005-ACCO changed to ACC0,OPH,OPL changed
--                            to DPH and DPL 
--                            ECN 863 ALEN brought forward to end of reset   
--                      1.004-ECN838 adjustment to OPC timing
--                           -and dummy address matching 
--                      1.003-Change to download mode
--                      1.002-File name changed from m3s000bo.vhd
--                      1.001(Original)
--
--
--
--*********************************************************************
--Hierarchy record      :
--Called by             :m8051_tb.vhd
--Calls to              :m3s001bo.vhd
--                      :m3s003bo.vhd
--                      :m3s004bo.vhd
--                      :m3s005bo.vhd
--                      :m3s006bo.vhd
--                      :m3s007bo.vhd
--                      :m3s008bo.vhd
--                      :m3s010bo.vhd
--                      :m3s015bo.vhd
--                      :m3s018bo.vhd
--                      :m3s019bo.vhd
--                      :m3s020bo.vhd
--                      :m3s023bo.vhd
--                      :m3s025bo.vhd
--                      :m3s028bo.vhd
--*********************************************************************
library IEEE;

use IEEE.std_logic_1164.all;
library WORK;

--*********************************************************************
--Entity Definition
--*********************************************************************
entity m8051 is 
--*******************************************************************       --
--IMPORTANT NOTICE                                                          --
--================                                                          --
--Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  --
--This file and associated deliverables are the trade secrets,              --
--confidential information and copyrighted works of Mentor Graphics         --
--Corporation and its licensors and are subject to your license agreement   --
--with Mentor Graphics Corporation.                                         --
--                                                                          --
--Use of these deliverables for the purpose of making silicon from an IC    --
--design is limited to the terms and conditions of your license agreement   --
--with Mentor Graphics If you have further questions please contact Mentor  --
--Graphics Customer Support.                                                --
--                                                                          --
--This Mentor Graphics core (m8051 v1999.120) was extracted on              --
--workstation hostid _hostid_ Inventra                                      --
       port(
            NMOE,
            NMWE,
            DLM,
            ALE,
            NPSEN,
            NALEN,
            NFWE,
            NFOE,
            NSFRWE,
            NSFROE,
            IDLE,
            XOFF:
            out std_logic;
            OA,
            OB,
            OC,
            OD,
            AE,
            BE,
            CE,
            DE,
            FA,
            FO:
            out std_logic_vector(7 downto 0);
            M:
            out std_logic_vector(15 downto 0);
            NX1,
            NX2,
            RST,
            NEA,
            NESFR,
            ALEI,
            PSEI:
            in std_logic;
            AI,
            BI,
            CI,
            DI,
            FI,
            MD:
            in std_logic_vector(7 downto 0)
            );
end m8051;
--*********************************************************************
--Architecture definition
--*********************************************************************
architecture m8051_rtl of m8051 is
--*********************************************************************
--*********************************************************************
--Component Definitions
--*********************************************************************
--Clock Generator
component m3s001bo
       port(STATD:
            out std_logic_vector(6 downto 1);
            CYC:
            out std_logic_vector(3 downto 1);
            LCYC,
            DIV2CK1,
            DIV2CK2,
            S_EN,
            T_EN,
            STATE12: 
            out std_logic;
            RST,
            GOCYC2,
            MULDIV,
            NX1,
            NX2:
            in std_logic;
            PCON:
            in std_logic_vector(0 downto 0)
            );
end component;
--*********************************************************************
--ALU
component m3s003bo
       port(ALUDAT,
            CPRDDM:
            out std_logic_vector(7 downto 0);
            CO,
            ACO,
            OV,
            BBIT:
            out std_logic;
            ACLDAT:
            in std_logic_vector(9 downto 0);         
            TMPDAT:
            in std_logic_vector(7 downto 0);
            ALUC:
            in std_logic_vector(17 downto 0);--bit 13 not used
            ACCDAT:
            in std_logic_vector(7 downto 7);
            BIT_POSN:
            in std_logic_vector(2 downto 0);
            NMULAB,
            NDIVAB,
            DAA,
            ACC0:
            in std_logic
            );
end component;
--*********************************************************************
--Opcode decode
component m3s004bo
       port(ACCADD:
            out std_logic_vector(9 downto 0);
            PCADD:
            out std_logic_vector(12 downto 1);
            REGADD:
            out std_logic_vector(10 downto 0);
            MOVX:
            out std_logic_vector(4 downto 0);
            ALUC: 
            out std_logic_vector(17 downto 0);
            PSWC,
            CODAT:
            out std_logic_vector(2 downto 0);
            TMPADD,
            SPC:
            out std_logic_vector(3 downto 0);
            ADDR_11BIT,
            JMPADPTR,
            LOGDI,
            GOCYC2,
            MULDIV,
            NMULAB,
            NDIVAB,
            DAA,
            CJNE,
            RETI,
            EITHER_RET,
            RMW,
            JBC,
            IMMB3,
            IMMB4:
            out std_logic;
            OPC:
            in std_logic_vector(7 downto 0);
            DAAL,
            DAAH:
            in std_logic
            );
end component;
--*********************************************************************
--Accumulator and ALU Input Temporary Register Number 2
component m3s005bo
      port(ACCDAT,
            BREG:
            out std_logic_vector(7 downto 0);
            ACLDAT:
            out std_logic_vector(9 downto 0);
            PAR,
            ACC0,
            DAAL,
            DAAH:
            out std_logic;
            CYC:
            in std_logic_vector(1 downto 1);
            PSWDAT:
            in std_logic_vector(7 downto 6);
            STATD:
            in std_logic_vector(6 downto 2);-- note bit 4 not used
            ACCADD:
            in std_logic_vector(9 downto 0);        
            ALUDAT,
            CPRDDM,
            RDAT,
            IMMDAT,
            RAMDI:
            in std_logic_vector(7 downto 0);
            SFRW:
            in std_logic_vector(21 downto 20);
            DAA,
            LCYC,
            DIV2CK,
            CO,
            RST,
            NX1:
            in std_logic
            ); 
end component;
--*********************************************************************
-- ALU Input Temporary Register Number 1
component m3s006bo
       port(TMPDAT:
            out std_logic_vector(7 downto 0);
            PROGRAM_COUNT:
            in std_logic_vector(15 downto 0);
            RDAT,
            IMMDAT,
            DPH,
            DPL,
            BREG:
            in std_logic_vector(7 downto 0);
            TMPADD:
            in std_logic_vector(3 downto 0);
            CODAT:
            in std_logic_vector(2 downto 0);
            CYC:
            in std_logic_vector(1 downto 1);
            STATD:
            in std_logic_vector(5 downto 2);
            LOGDI,
            DIV2CK,
            NX1,
            RST:
            in std_logic 
            );
end component;
--*********************************************************************
--Conditional Branch Test
component m3s007bo
       port(C_TRUE:
            out std_logic;
            ALUDAT:
            in std_logic_vector(7 downto 0);
            OPC:
            in std_logic_vector(7 downto 4);
            PSWDAT:
            in std_logic_vector(7 downto 7);
            CYC:
            in std_logic_vector(2 downto 2);
            STATD:
            in std_logic_vector(3 downto 3);
            BBIT,
            DIV2CK,
            NX1,
            RST:
            in std_logic 
            );    
end component;
--*********************************************************************
--Register control
component m3s008bo
       port(WEP,
            NFOE,
            NFWE,            
            NSFROE,
            NSFRWE:
            out std_logic;
            BIT_POSN:
            out std_logic_vector(2 downto 0);
            RAMDI,
            FA,
            RDAT:
            out std_logic_vector(7 downto 0);
            SFRW:
            out std_logic_vector(21 downto 0);
            JBC,
            EITHER_RET,
            C_TRUE,
            NESFR,
            CLEAR,
            LCYC,
            RESINT,
            DIV2CK,
            NX1,
            RST:
            in std_logic;
            ALUDAT,
            IMMDAT,
            SFRDAT,
            SP,
            IROMD,
            FI:
            in std_logic_vector(7 downto 0);
            CYC:
            in std_logic_vector(2 downto 1);
            OPC:
            in std_logic_vector(3 downto 0);
            PSWDAT:
            in std_logic_vector(4 downto 3);
            REGADD:
            in std_logic_vector(10 downto 0);
            STATD:
            in std_logic_vector(6 downto 1);
            STACK_DATA:
            in std_logic_vector(15 downto 0)
            );
end component;
--*********************************************************************
--Program counter control
component m3s010bo
       port(EXT_PROG_EN,
            EXT_ROM:            
            out std_logic;
            DPL,
            DPH:
            out std_logic_vector(7 downto 0);
            STACK_DATA,
            PROGRAM_COUNT,
            PROGRAM_ADDR:
            out std_logic_vector(15 downto 0);
            NEA,
            LCYC,
            DLM,
            DLMSTB,
            INTA,
            IDLE,
            C_TRUE,
            ADDR_11BIT,
            JMPADPTR,
            CLEAR,
            DIV2CK,
            NX1:
            in std_logic;