m3s002bo.vhd

来自「another 8051 core porocesssor vhdl sourc」· VHDL 代码 · 共 121 行

--*******************************************************************       --
--IMPORTANT NOTICE                                                          --
--================                                                          --
--Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  --
--This file and associated deliverables are the trade secrets,              --
--confidential information and copyrighted works of Mentor Graphics         --
--Corporation and its licensors and are subject to your license agreement   --
--with Mentor Graphics Corporation.                                         --
--                                                                          --
--Use of these deliverables for the purpose of making silicon from an IC    --
--design is limited to the terms and conditions of your license agreement   --
--with Mentor Graphics If you have further questions please contact Mentor  --
--Graphics Customer Support.                                                --
--                                                                          --
--This Mentor Graphics core (m8051 v1999.120) was extracted on              --
--workstation hostid _hostid_ Inventra                                      --
--M8051 ALU element
--Copyright Mentor Graphics Corporation and Licensors 1998. All Rights reserved.
--v1.003
--*********************************************************************
--@(#)m3s002bo.vhd	1.2 04/08/99 SCCS Version Control

--File	        :       m3s002bo.vhd
--Created on    :       1st Oct 1995
--Purpose       :       M8051 Megamacro ALU element 
--Version       :       1.003
--Mod Date      :       2nd April 1998
--Mod History	:	1.003 _e suffix removed from entity names.
--                      1.002 Comments updated.
--
--*********************************************************************
--Hierarchy record      :
--Called by             :m3s003bo.vhd
--Calls to              :None
--*********************************************************************
library IEEE;

use IEEE.std_logic_1164.all;
library WORK;

--*********************************************************************
--Entity Definition
--*********************************************************************

entity m3s002bo is 
--*******************************************************************       --
--IMPORTANT NOTICE                                                          --
--================                                                          --
--Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  --
--This file and associated deliverables are the trade secrets,              --
--confidential information and copyrighted works of Mentor Graphics         --
--Corporation and its licensors and are subject to your license agreement   --
--with Mentor Graphics Corporation.                                         --
--                                                                          --
--Use of these deliverables for the purpose of making silicon from an IC    --
--design is limited to the terms and conditions of your license agreement   --
--with Mentor Graphics If you have further questions please contact Mentor  --
--Graphics Customer Support.                                                --
--                                                                          --
--This Mentor Graphics core (m8051 v1999.120) was extracted on              --
--workstation hostid _hostid_ Inventra                                      --
       port(P,
            CO:
            out std_logic;
            ALUC:
            in std_logic_vector(5 downto 0);
            A,
            B:
            in std_logic
            );
end m3s002bo;
--*********************************************************************
--Architecture definition
--*********************************************************************
architecture m3s002bo_rtl of m3s002bo is
--*********************************************************************
signal AA,AB,AC,AD,AE,AF:std_logic;
--*********************************************************************
begin
--Notes
--SINGLE BIT ALU ELEMENT. ALUC CARRIES THE OPERATION CODE
--P IS THE PRODUCT.
--CO IS THE CARRY/BORROW OUT (NOTE BORROW IS INVERTED).
--OPERATION CODE
--      0 1 2 3 4 5 | OUTPUT
--      ------------+-------------
--      0 0 0 0 X X | 0
--      1 1 0 0 X X | NOT A
--      0 1 1 1 X X | A + B
--      0 1 0 1 X X | A EXOR B
--      0 0 1 1 X X | A
--      0 0 1 0 X X | A . B
--      1 0 1 0 X X | A - B
--      0 1 1 0 X X | B
--      X X X X 1 X | ENABLE CARRY
--      X X X X X 1 | ENABLE BORROW
--*********************************************************************
-- Process Definitions
--*********************************************************************
misc1:process(A, B, ALUC)
begin
   AA <= not A and not B and ALUC(0);
   AB <= not A and B and ALUC(1);
   AC <= A and B and ALUC(2);
   AD <= A and not B and ALUC(3);
   AE <= A and B and ALUC(4);
   AF <= A and not B and ALUC(5);
end process misc1;
--*********************************************************************
misc2:process(AA,AB,AC,AD,AE,AF)
begin
   P <= AA or AB or AC or AD;
   CO <= AE or AF;
end process misc2;
--*********************************************************************
--*********************************************************************
end m3s002bo_rtl;
--*********************************************************************