m3s008bo.vhd

来自「another 8051 core porocesssor vhdl sourc」· VHDL 代码 · 共 441 行 · 第 1/2 页

--*******************************************************************       --
--IMPORTANT NOTICE                                                          --
--================                                                          --
--Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  --
--This file and associated deliverables are the trade secrets,              --
--confidential information and copyrighted works of Mentor Graphics         --
--Corporation and its licensors and are subject to your license agreement   --
--with Mentor Graphics Corporation.                                         --
--                                                                          --
--Use of these deliverables for the purpose of making silicon from an IC    --
--design is limited to the terms and conditions of your license agreement   --
--with Mentor Graphics If you have further questions please contact Mentor  --
--Graphics Customer Support.                                                --
--                                                                          --
--This Mentor Graphics core (m8051 v1999.120) was extracted on              --
--workstation hostid _hostid_ Inventra                                      --
-- RAM and Special Function Register Controller for M8051
--Copyright Mentor Graphics Corporation and Licensors 1998. All rights reserved
--v2.001
--*********************************************************************
--@(#)m3s008bo.vhd	1.2 04/08/99 SCCS Version Control

--File	        :       m3s008bo.vhd
--Created on    :       14th March 1997
--Purpose       :       RAM and SFR controller for M8051
--Version       :       2.001
--Mod Date      :       2nd April 1998 
--Mod History	:       2.001 _e suffix removed from entity names.
--                      2.000 Re-written for SFR Expansion Capability,
--                            FA and FO outputs registered,
--                            redundancy removed from SFR control.
--                      1.006 Stack read address setup time advanced for
--                            second half of RET instructions.
--                            Direct register bank address generation
--                            simplified.
--                            Bit mode address generator moved.
--                            Sensitivity list revisions.
--			1.005 ECN 878: C_TRUE controls JBC writeback
--                            directly. Direct register bank write backs
--                            now take place at s4p2 in cycle 2.
--                            Indirect addresses stored in separate
--                            register: Ind_Addr.  Data write time
--                            restored to end of S6P2.
--                      1.004 Change to define FA during reset
--                      1.003 Timing correction 
--                      1.002 Calling file name changed to m8051.vhd
--                      1.001 Original
--
--
--
--*********************************************************************
--Hierarchy record      :
--Called by             :m8051.vhd
--                      :
--                      :
--Calls to              :m3s009bo.vhd
--                      :m3s039bo.vhd
--*********************************************************************
library IEEE;

use IEEE.std_logic_1164.all;
library WORK;

--*********************************************************************
--Entity Definition
--*********************************************************************

entity m3s008bo is 
--*******************************************************************       --
--IMPORTANT NOTICE                                                          --
--================                                                          --
--Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  --
--This file and associated deliverables are the trade secrets,              --
--confidential information and copyrighted works of Mentor Graphics         --
--Corporation and its licensors and are subject to your license agreement   --
--with Mentor Graphics Corporation.                                         --
--                                                                          --
--Use of these deliverables for the purpose of making silicon from an IC    --
--design is limited to the terms and conditions of your license agreement   --
--with Mentor Graphics If you have further questions please contact Mentor  --
--Graphics Customer Support.                                                --
--                                                                          --
--This Mentor Graphics core (m8051 v1999.120) was extracted on              --
--workstation hostid _hostid_ Inventra                                      --
       port(WEP,
            NFOE,
            NFWE,            
            NSFROE,
            NSFRWE:            
            out std_logic;
            BIT_POSN:
            out std_logic_vector(2 downto 0);
            RAMDI,
            FA,
            RDAT:
            out std_logic_vector(7 downto 0);
            SFRW:
            out std_logic_vector(21 downto 0);
            JBC,
            EITHER_RET,
            C_TRUE,
            NESFR,
            CLEAR,
            LCYC,
            RESINT,
            DIV2CK,
            NX1,
            RST:
            in std_logic;
            ALUDAT,
            IMMDAT,
            SFRDAT,
            SP,
            IROMD,
            FI:
            in std_logic_vector(7 downto 0);
            CYC:
            in std_logic_vector(2 downto 1);
            OPC:
            in std_logic_vector(3 downto 0);
            PSWDAT:
            in std_logic_vector(4 downto 3);
            REGADD:
            in std_logic_vector(10 downto 0);
            STATD:
            in std_logic_vector(6 downto 1);
            STACK_DATA:
            in std_logic_vector(15 downto 0)
            );
end m3s008bo;
--*********************************************************************

--Architecture definition
--*********************************************************************
architecture m3s008bo_rtl of m3s008bo is
--*********************************************************************
--*********************************************************************
-- Component Definitions
--*********************************************************************
--Register mux
component m3s009bo
       port(RAMDI:
            out std_logic_vector(7 downto 0);
            STACK_DATA:
            in std_logic_vector(15 downto 0);
            IMMDAT,
            ALUDAT:
            in std_logic_vector(7 downto 0);
            REGADD:
            in std_logic_vector(1 downto 0);
            CYC:
            in std_logic_vector(2 downto 2);
            STATD:
            in std_logic_vector(5 downto 5);
            RDAT:
            in std_logic_vector(7 downto 4);
            DIV2CK,
            NX1,
            RST:
            in std_logic 
            );
end component;
--*********************************************************************
--SFR write strobe decoder sub-module
component m3s039bo
       port(
            SFRW:
            out std_logic_vector(21 downto 0);
            WEP:
            out std_logic;
            FA:
            in std_logic_vector(6 downto 0);
            SFR_LOAD,
            SFRWE:
            in std_logic
            );
end component;
--*********************************************************************
--*********************************************************************
--signal definition
--*********************************************************************
signal FA_EN, SFR_LOAD, SEL_SFR_NRAM, JBC_FAILED: std_logic;
signal FOE, FWE, SFROE, SFRWE: std_logic;
signal SEL_DIRADDR, SEL_STACKPTR, SEL_INDADDR, SEL_REGBANK: std_logic;
signal L_FA, L_RDAT, ASYNC_RAMDI: std_logic_vector(7 downto 0);
signal INDIRECT_ADDR, DIRECT_ADDR: std_logic_vector(7 downto 0);
signal REG_BANK_ADDR, BIT_MODE_ADDR: std_logic_vector(7 downto 0);
signal NEXT_FA: std_logic_vector(7 downto 0);
--*********************************************************************
--*********************************************************************
--port mapping
--*********************************************************************
begin
--*********************************************************************
U1:m3s009bo
  port map(
           RAMDI => ASYNC_RAMDI,
           STACK_DATA => STACK_DATA,
           IMMDAT => IMMDAT,
           ALUDAT => ALUDAT,
           REGADD => REGADD(1 downto 0),
           CYC(2 downto 2) => CYC(2 downto 2),
           STATD(5 downto 5) => STATD(5 downto 5), 
           RDAT => L_RDAT(7 downto 4),
           DIV2CK => DIV2CK,
           NX1 => NX1,
           RST => RST
           );
--*********************************************************************
U2:m3s039bo
  port map(
           SFRW => SFRW,
           WEP => WEP,
           FA => L_FA(6 downto 0),
           SFR_LOAD => SFR_LOAD,
           SFRWE => SFRWE
           );
--*********************************************************************

--*********************************************************************
--Process Definitions