m3s015bo.vhd

来自「another 8051 core porocesssor vhdl sourc」· VHDL 代码 · 共 486 行 · 第 1/2 页

           LTCON3 <='0';
           TCON(5) <='0';
           TCON(7) <='0';
       else 
           if IACK(0) ='0' then
                LTCON1 <= '0';
           elsif TCON1SET ='1' then
                LTCON1 <= '1';
           elsif SFRW(4) = '1' then
                LTCON1 <= RAMDI(1);
           end if;

           if IACK(2) ='0' then
                LTCON3 <= '0';
           elsif TCON3SET ='1' then
                LTCON3 <= '1';
           elsif SFRW(4) = '1' then
                LTCON3 <= RAMDI(3);
           end if; 

           if IACK(1) ='0' then
                 TCON(5) <= '0';
           elsif DIV2CK1 = '0' then
              if (LOV0  and (S_EN or (RMW and STATD(6)))) = '1' then
                 TCON(5) <= '1';
              elsif SFRW(4) = '1' then
                 TCON(5) <= RAMDI(5);
              end if;
           end if; 


           if IACK(3) ='0' then
              TCON(7) <= '0';
           elsif DIV2CK1 = '0' then
              if  (LLOV1 and (S_EN or (RMW and STATD(6)))) = '1' then
                 TCON(7) <= '1';
              elsif SFRW(4) = '1' then
                 TCON(7) <= RAMDI(7);
              end if; 
           end if; 
       end if;
    end if;
end process tconodd;
--*********************************************************************
selecttcon1:process(LTCON0,LTCON1,INT0, OLD_INT0)
begin
   case LTCON0 is
       when '0' => TCON(1) <= INT0 or OLD_INT0;
       when '1' => TCON(1) <= LTCON1;
       when others => TCON(1) <= 'X';
    end case;
end process selecttcon1;   
--*********************************************************************
selecttcon3:process(LTCON2,LTCON3,INT1, OLD_INT1)
begin
   case LTCON2 is
       when '0' => TCON(3) <= INT1 or OLD_INT1;
       when '1' => TCON(3) <= LTCON3;
       when others => TCON(3) <= 'X';
    end case;
end process selecttcon3;   
--*********************************************************************
p3sampler:process(NX1)
-- External input sampling flip-flops.  All four port inputs are sampled on S5P2
begin
    if NX1'event and NX1 ='1' then
       if CLEAR='1' then
          INT0     <= '0';
          INT1     <= '0';
          T0       <= '0';
          T1       <= '0';
          OLD_INT0 <= '0';
          OLD_INT1 <= '0';
          OLD_T0   <= '0';
          OLD_T1   <= '0';
       elsif (DIV2CK1='0' and S_EN='1') then
          INT0     <= not DI(2);
          INT1     <= not DI(3);
          T0       <= DI(4);
          T1       <= DI(5);
          OLD_INT0 <= INT0;
          OLD_INT1 <= INT1;
          OLD_T0   <= T0;
          OLD_T1   <= T1;
       end if;
    end if;
end process p3sampler;
--*********************************************************************
set_cnt2:process(T0, T1, OLD_T0, OLD_T1)
-- External counter input falling edge detectors
begin
   CNT0 <= OLD_T0 and not T0;
   CNT1 <= OLD_T1 and not T1;
end process set_cnt2;
--*********************************************************************
tconsetclr:process(INT0, INT1, OLD_INT0, OLD_INT1)
-- External interrupt falling edge detectors
begin 
   TCON1SET <= INT0 and not OLD_INT0;
   TCON3SET <= INT1 and not OLD_INT1;
end process tconsetclr;
--*********************************************************************
synch_ov0: process(NX1) -- convert counter timer 0 carry out to overflow
-- Interrupt source is set at timer oveflow (end of S2P2) and cleared at
-- end of S6P2.
begin
   if NX1'event and NX1 = '1' then
      if T0L_EN = '1' then
         LOV0 <= ILOV0;
      elsif STATE12 = '1' then
         LOV0 <= '0';
      end if;
   end if;
end process synch_ov0;
--*********************************************************************
synch_ov1: process(NX1) -- convert counter timer 1 carry out to overflow
-- Interrupt source is set at timer oveflow (end of S2P2) and cleared at
-- end of S6P2.
begin
   if NX1'event and NX1 = '1' then
      if OV1_EN = '1' then
         LLOV1 <= ILOV1;
      elsif STATE12 = '1' then
         LLOV1 <= '0';
      end if;
   end if;
end process synch_ov1;
--*********************************************************************
settmod:process(NX2)
begin
    if NX2'event and NX2 ='1' then
        if CLEAR ='1' then
            LTMOD(7 downto 0) <= "00000000";
        elsif SFRW(5) = '1' then
            LTMOD(7 downto 0) <= RAMDI(7 downto 0);          
        end if;
    end if;
end process settmod;
--*********************************************************************
set_mods:process(LTMOD)
begin
    MODL0 <= not(LTMOD(0) or LTMOD(1));
    MODL1 <= not(LTMOD(4) or LTMOD(5));
end process set_mods;
--*********************************************************************
--*********************************************************************
timertims:process(T_EN,DIV2CK1)
begin
       TIMERS_EN <= T_EN and not DIV2CK1;
end process timertims;
--*********************************************************************
timcntenabs:process(LTMOD, TIMERS_EN, T1_MODE3, CNT0, CNT1)
-- Timer Counters increment on S3P1 regardless of mode.
-- Timer Counter 1 does not count in mode 3.
begin
   COUNTER0_EN <= TIMERS_EN and LTMOD(2) and CNT0; 
   COUNTER1_EN <= TIMERS_EN and LTMOD(6) and CNT1 and not T1_MODE3; 
   TIMER0_EN <=   TIMERS_EN and not LTMOD(2); 
   TIMER1_EN <=   TIMERS_EN and not LTMOD(6) and not T1_MODE3; 
end process timcntenabs;
--*********************************************************************
timer_en:process(COUNTER0_EN,COUNTER1_EN,TIMER0_EN,TIMER1_EN,TIMERS_EN, T0_MODE3, SFRW)
begin
   T0L_EN <= COUNTER0_EN or TIMER0_EN or SFRW(6);
   T0H_EN <= (not(T0_MODE3) and (COUNTER0_EN or TIMER0_EN)) or 
             (T0_MODE3 and TIMERS_EN) or SFRW(8);
   T1_EN <= COUNTER1_EN or TIMER1_EN or SFRW(7) or SFRW(9);
end process timer_en;
--*********************************************************************
overflow1_en:process(T0H_EN, T1_EN, T0_MODE3)
-- MUX for replacing T1_EN with T0H_EN as clock source for overflow
-- register in mode 3.
begin
   OV1_EN <= (T1_EN and not T0_MODE3) or (T0H_EN and T0_MODE3);  
end process overflow1_en;
--*********************************************************************
set_nci:process(LTMOD, T0_MODE3, LTCON4, LTCON6, INT0, INT1, COL0,
                COL1, STATD)
-- Define carry inputs to the four 8-bit counters.
-- Mask carry inputs during SFR write window (end STATD(6)).
begin
   CIL0 <= LTCON4 and (not(LTMOD(3)) or not INT0) and not STATD(6);
   CIL1 <= LTCON6 and (not(LTMOD(7)) or not INT1) and not STATD(6);
   CIH0 <= ((COL0 and not LTMOD(1)) or (T0_MODE3 and LTCON6))
           and not STATD(6);
   CIH1 <= COL1 and not LTMOD(5) and not STATD(6); 
end process set_nci;
--*********************************************************************
set_ilov:process(COH0,COL0,COL1,COH1,LTMOD,CLEAR,AB,AC)
begin 
   ILOV0 <= ((COH0 and not LTMOD(1)) or (COL0 and LTMOD(1)))
            and not CLEAR;    
   ILOV1 <= ((COH1 and not AC) or (COL1 and not AB) or(COH0 and LTMOD(0)
            and LTMOD(1))) and not CLEAR;
end process set_ilov;
--*********************************************************************
set_low_byte_load:process(SFRW, LTMOD, COL0, COL1)
-- Low byte counter load control is OR of SFR write signal and in mode 2
-- the low byte overflow.
begin
   LOAD0 <= SFRW(6) or ( LTMOD(1) and not LTMOD(0) and COL0 );
   LOAD1 <= SFRW(7) or ( LTMOD(5) and not LTMOD(4) and COL1 );
end process set_low_byte_load;
--*********************************************************************
set_din:process(RAMDI,LTHA,LTHB,SFRW)
begin
case SFRW(6) is
       when '0' => DINA <= LTHA;
       when '1' => DINA <= RAMDI;
       when others => DINA <= "XXXXXXXX";
    end case;
case SFRW(7) is
       when '0' => DINB <= LTHB;
       when '1' => DINB <= RAMDI;
       when others => DINB <= "XXXXXXXX";
    end case;
end process set_din;
--*********************************************************************
misc1:process(LTMOD)
begin
   T0_MODE3 <= LTMOD(0) and LTMOD(1);
   T1_MODE3 <= LTMOD(4) and LTMOD(5);
end process misc1;
--*********************************************************************
localout:process(LTCON0,LTCON2,LTCON4,LTCON6,LTHA,LTHB,LTMOD,ILOV1,S_EN, LLOV1)
begin
   TCON(0) <= LTCON0;
   TCON(2) <= LTCON2;
   TCON(4) <= LTCON4;
   TCON(6) <= LTCON6;
   THA <= LTHA;
   THB <= LTHB;
   TMOD(7 downto 0) <= LTMOD(7 downto 0);
   LOV1 <= LLOV1 and S_EN;
end process localout;
--*********************************************************************

LOGIC0 <= '0';

--*********************************************************************
end m3s015bo_rtl;
--*********************************************************************