m3s015bo.vhd

来自「another 8051 core porocesssor vhdl sourc」· VHDL 代码 · 共 486 行 · 第 1/2 页

--*******************************************************************       --
--IMPORTANT NOTICE                                                          --
--================                                                          --
--Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  --
--This file and associated deliverables are the trade secrets,              --
--confidential information and copyrighted works of Mentor Graphics         --
--Corporation and its licensors and are subject to your license agreement   --
--with Mentor Graphics Corporation.                                         --
--                                                                          --
--Use of these deliverables for the purpose of making silicon from an IC    --
--design is limited to the terms and conditions of your license agreement   --
--with Mentor Graphics If you have further questions please contact Mentor  --
--Graphics Customer Support.                                                --
--                                                                          --
--This Mentor Graphics core (m8051 v1999.120) was extracted on              --
--workstation hostid _hostid_ Inventra                                      --
--Timer Counters for M8051
--Copyright Mentor Graphics Corporation and Licensors 1998. All rights reserved.
--v1.007
--*********************************************************************
--@(#)m3s015bo.vhd	1.2 04/08/99 SCCS Version Control

--File	        :       m3s015bo.vhd
--Created on    :       24th Oct 1995
--Purpose       :       Timer Counter for M8051
--Version       :       1.007
--Mod Date      :       7th October 1998
--                      1.007 NINT0/1 sampling time restricted to S5P2
--                      1.006 _e suffix removed from entity names.
--                      1.005 Redundant signals removed, name change,
--                            re-load false path removed.
--                      1.004 Overflow synchronising flip-flops
--                            re-instated, TH0 clock source fix,
--                            timer 1 enable logic,
--                            external interrupt sampling flip-flops,
--                            RMW instructions prevented from erasing
--                            pending timer interrupts.
--                            Level sensitive interrupts now sampled
--                            and registered at end of S5P2.
--                            Sensitivity list revisions.
--			1.003 Idle Mode Power Saving.
--			1.002 Calling file name changed to m8051.vhd
--                      1.001 Original
--
--*********************************************************************
--Hierarchy record      :
--Called by             :m8051.vhd
--                      :
--                      :
--Calls to              :m3s016bo.vhd
--                      :m3s017bo.vhd
--*********************************************************************
library IEEE;

use IEEE.std_logic_1164.all;
library WORK;
--*********************************************************************
--Entity Definition
--*********************************************************************

entity m3s015bo is 
--*******************************************************************       --
--IMPORTANT NOTICE                                                          --
--================                                                          --
--Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  --
--This file and associated deliverables are the trade secrets,              --
--confidential information and copyrighted works of Mentor Graphics         --
--Corporation and its licensors and are subject to your license agreement   --
--with Mentor Graphics Corporation.                                         --
--                                                                          --
--Use of these deliverables for the purpose of making silicon from an IC    --
--design is limited to the terms and conditions of your license agreement   --
--with Mentor Graphics If you have further questions please contact Mentor  --
--Graphics Customer Support.                                                --
--                                                                          --
--This Mentor Graphics core (m8051 v1999.120) was extracted on              --
--workstation hostid _hostid_ Inventra                                      --
       port(LOV1:
            out std_logic;
            TCON,
            TMOD,
            TLA,
            TLB,
            THA,
            THB:
            out std_logic_vector(7 downto 0);
            IACK:
            in std_logic_vector(3 downto 0);
            DI:
            in std_logic_vector(5 downto 2);
            STATD:
            in std_logic_vector(6 downto 6);
            RAMDI:
            in std_logic_vector(7 downto 0);
            SFRW:
            in std_logic_vector(9 downto 4);
            RMW,
            S_EN,
            T_EN,
            STATE12,
            DIV2CK1,
            NX1,
            NX2,
            CLEAR:
            in std_logic
            );
end m3s015bo;
--*********************************************************************
--Architecture definition
--*********************************************************************
architecture m3s015bo_rtl of m3s015bo is
--*********************************************************************
--*********************************************************************
-- Component Definition
--*********************************************************************
--8 bit loadable counter with carry out from fifth or eighth bit.
component m3s016bo
       port(
            CO:            
            out std_logic;
            CNT:
            out std_logic_vector(7 downto 0);
            MODE0,
            LD,
            CI,
            CLEAR,
            COUNT_EN,
            NX1:
            in std_logic;
            DIN:
            in std_logic_vector(7 downto 0)
            );
end component;
--*********************************************************************
--signal definition
--*********************************************************************
signal COH0,COH1,COL0,COL1,CIH0,CIH1,CIL0,CIL1,MODL0,MODL1:std_logic;
signal T0L_EN,T0H_EN,T1_EN, OV1_EN, CNT0,CNT1,T0_MODE3,T1_MODE3:std_logic;
signal LOAD0,LOAD1,ILOV0,ILOV1:std_logic;
signal LTCON0,LTCON1,LTCON2,LTCON3,LTCON4,LTCON6:std_logic;
signal TCON1SET,TCON3SET:std_logic;
signal AB,AC:std_logic;
signal LTMOD,LTHA,LTHB,DINA,DINB:std_logic_vector(7 downto 0);
signal COUNTER0_EN, COUNTER1_EN,TIMER0_EN,TIMER1_EN,TIMERS_EN:std_logic;
signal LOV0, LLOV1: std_logic; -- synchronised timer overflow registers
signal INT0, INT1: std_logic; -- sampled external interrupt inputs
signal OLD_INT0, OLD_INT1: std_logic; -- external interrupt memories
signal T0, T1, OLD_T0, OLD_T1:std_logic; -- sampled counter inputs
signal LOGIC0: std_logic;

--*********************************************************************
--*********************************************************************
--port mapping
--*********************************************************************
begin
--*********************************************************************
U1:m3s016bo --Timer zero high byte
  port map(
           CO => COH0,           
           CNT => LTHA,
           MODE0 => LOGIC0,
           LD =>  SFRW(8),
           CI => CIH0,
           CLEAR => CLEAR,
           COUNT_EN => T0H_EN,
           NX1 => NX1,
           DIN => RAMDI
           );
--*********************************************************************
U2:m3s016bo --Timer one high byte
  port map(
           CO => COH1,           
           CNT => LTHB,
           MODE0 => LOGIC0,
           LD =>  SFRW(9),
           CI => CIH1,
           CLEAR => CLEAR,
           COUNT_EN => T1_EN,
           NX1 => NX1,
           DIN => RAMDI
           );
--*********************************************************************
U3:m3s016bo -- Timer zero low byte
  port map(
           CO => COL0,           
           CNT => TLA,
           MODE0 => MODL0,
           LD => LOAD0,
           CI => CIL0,
           CLEAR => CLEAR,
           COUNT_EN => T0L_EN,
           NX1 => NX1,
           DIN => DINA
           );
--*********************************************************************
U4:m3s016bo -- Timer one low byte
  port map(
           CO => COL1,           
           CNT => TLB,
           MODE0 => MODL1,
           LD => LOAD1,
           CI => CIL1,
           CLEAR => CLEAR,
           COUNT_EN => T1_EN,
           NX1 => NX1,
           DIN => DINB
           );
--*********************************************************************

--*********************************************************************
--Process Definitions 
--*********************************************************************
tconeven:process(NX2)
begin
    if NX2'event and NX2 ='1' then
        if CLEAR ='1' then
            LTCON0 <= '0';
            LTCON2 <= '0';
            LTCON4 <= '0';
            LTCON6 <= '0';
        elsif SFRW(4) = '1' then
            LTCON0 <= RAMDI(0);
            LTCON2 <= RAMDI(2);
            LTCON4 <= RAMDI(4);
            LTCON6 <= RAMDI(6);           
        end if;
    end if;
end process tconeven;
--*********************************************************************
gen1:process(LTMOD)
begin
   AB <= LTMOD(4) or (LTMOD(0) and LTMOD(1)) or not LTMOD(5);
   AC <= LTMOD(5) or (LTMOD(0) and LTMOD(1));
end process gen1;
--*********************************************************************
tconodd:process(NX1)
-- TCON odd bits may be set at S5P2 by interrupt sources
-- Interrupts may be overwritten by direct register load instructions,
-- but not by read-modify-write instructions.
begin
    if NX1'event and NX1 ='1' then
       if CLEAR ='1' then 
           LTCON1 <='0';