m3s010bo.vhd

来自「another 8051 core porocesssor vhdl sourc」· VHDL 代码 · 共 417 行 · 第 1/2 页

--*******************************************************************       --
--IMPORTANT NOTICE                                                          --
--================                                                          --
--Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  --
--This file and associated deliverables are the trade secrets,              --
--confidential information and copyrighted works of Mentor Graphics         --
--Corporation and its licensors and are subject to your license agreement   --
--with Mentor Graphics Corporation.                                         --
--                                                                          --
--Use of these deliverables for the purpose of making silicon from an IC    --
--design is limited to the terms and conditions of your license agreement   --
--with Mentor Graphics If you have further questions please contact Mentor  --
--Graphics Customer Support.                                                --
--                                                                          --
--This Mentor Graphics core (m8051 v1999.120) was extracted on              --
--workstation hostid _hostid_ Inventra                                      --
--Program Counter Control for M8051
--Copyright Mentor Graphics Corporation and Licensors 1998. All rights reserved
--v1.010
--*********************************************************************
--@(#)m3s010bo.vhd	1.2 04/08/99 SCCS Version Control

--File	        :       m3s010bo.vhd
--Created on    :       28th Dec 1995
--Purpose       :       PC control for M8051
--Version       :       1.010
--Mod Date      :       2nd April 1998
--Mod History	:       1.010 _e suffix removed from entity names.
--                      1.009 STATDs 7-12 abandoned, redundant nets
--                            excised.
--                      1.008 Name change for Verilog translation
--                      1.007 PC MUX controls re-written for synthesis.
--                            EXT_PROG_EN and MOVC MUX moved in from
--                            m3s018bo. Program address busses revised.
--                            Sensitivity list revisions.
--                      1.006 ECN 878: Fast decision path for jump
--                            relatives
--			1.006 Unconditional look-ahead vector generation
--			1.005 OPH and OPL changed to DPH and DPL
--                      1.004-ECN 838 adjustment of OPC timing and
--                            dummy address cycle matching
--                      1.003- Change for download mode
--                      1.002-Calling file name changed to m8051.vhd
--                            LADD output removed
--                      1.001(Original)
--
--
--
--*********************************************************************
--Hierarchy record      :
--Called by             :m8051.vhd
--                      :
--                      :
--Calls to              :m3s013bo.vhd
--                      :m3s011bo.vhd
--*********************************************************************
library IEEE;

use IEEE.std_logic_1164.all;
library WORK;

--*********************************************************************
--Entity Definition
--*********************************************************************

entity m3s010bo is 
--*******************************************************************       --
--IMPORTANT NOTICE                                                          --
--================                                                          --
--Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  --
--This file and associated deliverables are the trade secrets,              --
--confidential information and copyrighted works of Mentor Graphics         --
--Corporation and its licensors and are subject to your license agreement   --
--with Mentor Graphics Corporation.                                         --
--                                                                          --
--Use of these deliverables for the purpose of making silicon from an IC    --
--design is limited to the terms and conditions of your license agreement   --
--with Mentor Graphics If you have further questions please contact Mentor  --
--Graphics Customer Support.                                                --
--                                                                          --
--This Mentor Graphics core (m8051 v1999.120) was extracted on              --
--workstation hostid _hostid_ Inventra                                      --
       port(EXT_PROG_EN,
            EXT_ROM:            
            out std_logic;
            DPL,
            DPH:
            out std_logic_vector(7 downto 0);
            STACK_DATA,
            PROGRAM_COUNT,
            PROGRAM_ADDR:
            out std_logic_vector(15 downto 0);
            NEA,
            LCYC,
            DLM,
            DLMSTB,
            INTA,
            IDLE,
	    C_TRUE,
            ADDR_11BIT,
            JMPADPTR,
            CLEAR,
            DIV2CK,
            NX1:
            in std_logic;
            VECTOR_ADDR:
            in std_logic_vector(4 downto 1);
            RDAT,
            ALUDAT,
            IMMDAT,
            RAMDI,
            MSIZ:
            in std_logic_vector(7 downto 0);
            CYC:
            in std_logic_vector(2 downto 1);
            OPC:
            in std_logic_vector(7 downto 5);
            PCADD:
            in std_logic_vector(12 downto 1);
            STATD:
            in std_logic_vector(6 downto 1);
            SFRW:
            in std_logic_vector(15 downto 14)
            );
end m3s010bo;
--*********************************************************************
--Architecture definition
--*********************************************************************
architecture m3s010bo_rtl of m3s010bo is
--*********************************************************************
--*********************************************************************
-- Component Definitions
--*********************************************************************
--PC Inc/jump
component m3s011bo
       port(NEXT_REL_PC:
            out std_logic_vector(15 downto 0);
            PROGRAM_COUNT:
            in std_logic_vector(15 downto 0);
            IMMDAT:
            in std_logic_vector(7 downto 0);
            PC_INCR,
            JMP_REL:
            in std_logic
            );
end component;
--*********************************************************************
--pc mux
component m3s013bo
       port(NEXT_PROGRAM_COUNT:
            out std_logic_vector(15 downto 0);
            VECTOR_ADDR:
            in std_logic_vector(4 downto 1);
            IMMDAT,
            ALUDAT,
            RDAT:
            in std_logic_vector(7 downto 0);
            OPC:
            in std_logic_vector(7 downto 5);
            NEXT_REL_PC:
            in std_logic_vector(15 downto 0);
            PCADD:
            in std_logic_vector(2 downto 1);
            NFBL,
            NFBH,
            SEL_11BIT_ADDR,
            INTA:
            in std_logic
            );
end component;
--*********************************************************************
--*********************************************************************
--signal definitions
--*********************************************************************
signal AG, BA, JMP_REL, L_EXT_ROM, PC_INCR: std_logic;
signal NFBH, NFBL, SEL_11BIT_ADDR:std_logic;
signal PROGRAM_COUNT_EN, STACK_DATA_EN, DPL_EN, DPH_EN:std_logic;
signal DPTR_DATA,LOCALA: std_logic_vector(7 downto 0);
signal ADDR_16BIT_LOW: std_logic_vector(7 downto 0);
signal NEXT_PROGRAM_COUNT, NEXT_PROGRAM_ADDR:std_logic_vector(15 downto 0);
signal NEXT_REL_PC, L_PROGRAM_COUNT:std_logic_vector(15 downto 0);
--*********************************************************************
--*********************************************************************
--port mapping
--*********************************************************************
begin
--*********************************************************************
U1:m3s011bo
  port map(
            NEXT_REL_PC => NEXT_REL_PC,
            PROGRAM_COUNT => L_PROGRAM_COUNT,
            IMMDAT => IMMDAT,
            PC_INCR => PC_INCR,
            JMP_REL => JMP_REL
           );
--*********************************************************************
U2:m3s013bo
  port map(
           NEXT_PROGRAM_COUNT => NEXT_PROGRAM_COUNT,
           VECTOR_ADDR => VECTOR_ADDR,
           IMMDAT => IMMDAT,
           ALUDAT => ALUDAT,
           RDAT => RDAT,
           OPC => OPC,
           NEXT_REL_PC => NEXT_REL_PC,
           PCADD => PCADD(2 downto 1),
           NFBL => NFBL,
           NFBH => NFBH,
           SEL_11BIT_ADDR => SEL_11BIT_ADDR,