m3s004bo.vhd

来自「another 8051 core porocesssor vhdl sourc」· VHDL 代码 · 共 575 行 · 第 1/2 页

--*******************************************************************       --
--IMPORTANT NOTICE                                                          --
--================                                                          --
--Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  --
--This file and associated deliverables are the trade secrets,              --
--confidential information and copyrighted works of Mentor Graphics         --
--Corporation and its licensors and are subject to your license agreement   --
--with Mentor Graphics Corporation.                                         --
--                                                                          --
--Use of these deliverables for the purpose of making silicon from an IC    --
--design is limited to the terms and conditions of your license agreement   --
--with Mentor Graphics If you have further questions please contact Mentor  --
--Graphics Customer Support.                                                --
--                                                                          --
--This Mentor Graphics core (m8051 v1999.120) was extracted on              --
--workstation hostid _hostid_ Inventra                                      --
--Opcode Decoder for m8051
--Copyright Mentor Graphics Corporation and Licensors 1998. All rights reserved
--v1.008
--*********************************************************************
--@(#)m3s004bo.vhd	1.2 04/08/99 SCCS Version Control
--File	        :       m3s004bo.vhd
--Created on    :       23th September 1995
--Purpose       :       opcode decoder for m8051
--Version       :       1.008
--Mod Date      :       2nd April 1998
--Mod History	:       1.008 _e suffix removed from entity names.
--                      1.007 PSW carry enable restricted.
--                      1.006 Name change for Verilog translation
--                      1.005 Sensitivity list revisions.
--                      1.004 ECN 878: CTRU and INTA removed from
--                            decoder.  RMW definition widened to
--                            include register instructions.
--                      1.003 ECN 842 -ORLC timing adjustment, 
--                            ECN      dummy address matching 
--                      1.002 Calling file name changed to m8051.vhd
--                      1.001 Original
--
--*********************************************************************
--Hierarchy record      :
--Called by             :m8051.vhd
--Calls to              :None
--                      :
--                      :
--                      :
--*********************************************************************
library IEEE;

use IEEE.std_logic_1164.all;
library WORK;

--*********************************************************************
--Entity Definition
--*********************************************************************

entity m3s004bo is
--*******************************************************************       --
--IMPORTANT NOTICE                                                          --
--================                                                          --
--Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  --
--This file and associated deliverables are the trade secrets,              --
--confidential information and copyrighted works of Mentor Graphics         --
--Corporation and its licensors and are subject to your license agreement   --
--with Mentor Graphics Corporation.                                         --
--                                                                          --
--Use of these deliverables for the purpose of making silicon from an IC    --
--design is limited to the terms and conditions of your license agreement   --
--with Mentor Graphics If you have further questions please contact Mentor  --
--Graphics Customer Support.                                                --
--                                                                          --
--This Mentor Graphics core (m8051 v1999.120) was extracted on              --
--workstation hostid _hostid_ Inventra                                      --
       port(ACCADD:
            out std_logic_vector(9 downto 0);
            PCADD:
            out std_logic_vector(12 downto 1);
            REGADD:
            out std_logic_vector(10 downto 0);
            MOVX:
            out std_logic_vector(4 downto 0);
            ALUC: 
            out std_logic_vector(17 downto 0);
            CODAT,
            PSWC:
            out std_logic_vector(2 downto 0);
            TMPADD,
            SPC:
            out std_logic_vector(3 downto 0);
            ADDR_11BIT,
            JMPADPTR,
            LOGDI,
            GOCYC2,
            MULDIV,
            NMULAB,
            NDIVAB,
            DAA,
            CJNE,
            RETI,
            EITHER_RET,
            RMW,
            JBC,
            IMMB3,
            IMMB4:
            out std_logic;
            OPC:
            in std_logic_vector(7 downto 0);
            DAAL,
            DAAH:
            in std_logic
            );       
end m3s004bo;
--*********************************************************************
--Architecture definition
--*********************************************************************
architecture m3s004bo_rtl of m3s004bo is
--*********************************************************************
--*********************************************************************
--Component Definitions
--*********************************************************************
--Decode matrix
component m3s022bo
       port(LODEC:
            out std_logic_vector(7 downto 0);
            HIDEC:
            out std_logic_vector(15 downto 0);
            OPC: 
            in std_logic_vector(7 downto 0)
            );
end component;
--*********************************************************************
component m3s024bo
       port(ALUC:
            out std_logic_vector(17 downto 0);
            LODEC_4TOF,
            NDIVAB,
            NDJNZD,
            NDJNZR,
            NMULAB,
            DAA,
            NLJMP,
            NLCALL,
            NOP16,
            NCPLB,
            NSETB,
            NSETC,
            NORLCN,
            NORLCB,
            NMOVCB,
            NCLRB,
            NCLRC,
            NANLCN,
            NANLCB,
            JBC,
            NCPLC:
            out std_logic;
            HIDEC:
            in std_logic_vector(15 downto 0);
            LODEC: 
            in std_logic_vector(5 downto 0);
            OPC:
            in std_logic_vector(3 downto 1);
            RET,
            RETI:
            in std_logic 
            );       
end component;
--*********************************************************************
component m3s033bo
       port(ACCADD:
            out std_logic_vector(9 downto 0);
            NMOVPC,
            NINCDP,
            NSWAPN,
            NMOVBC,
            LOGDI:
            out std_logic;
            HIDEC:
            in std_logic_vector(14 downto 0);
            LODEC: 
            in std_logic_vector(7 downto 0);
            OPC:
            in std_logic_vector(7 downto 3);
            LODEC_4TOF,
            NOP16,
            MULDIV,
            INDXR,
            INDOP,
            NDIV,
            NDJD,
            NDJR,
            NBEN,
            CJNE,
            NMUL,
            NMCB:
            in std_logic 
            );       
end component;
--*********************************************************************
component m3s032bo
       port(TMPADD:
            out std_logic_vector(3 downto 0);
            PCLONG,
            LO5TOF,
            NLOGDA:
            out std_logic;
            HIDEC:
            in std_logic_vector(11 downto 2);
            LODEC: 
            in std_logic_vector(5 downto 2);
            LODEC_4TOF,
            ND16,
            MULDIV,
            NMPC,
            NLCA,
            NLJM,
            EITHER_RET,
            LOGDI:
            in std_logic 
            );       
end component;
--*********************************************************************
component m3s034bo
       port(PCADD:
            out std_logic_vector(12 downto 1);
            HIDEC:
            in std_logic_vector(15 downto 0);--bits 4 to 6 and 12,13 not used
            LODEC:
            in std_logic_vector(5 downto 0);
            OPC:
            in std_logic_vector(7 downto 3);--bits and 3 only used
            NLCALL,
            BRET,
            PCL0,
            DJNZ,
            CJNE,
            NIDP,
            INDOP,
            LOGDI,
            NDJR,
            NDJD:
            in std_logic 
            );       
end component;
--*********************************************************************
component m3s035bo
       port(REGADD:
            out std_logic_vector(10 downto 0);
            NCALL,
            NPOP,
            NPUSH:
            out std_logic;
            HIDA:
            in std_logic_vector(3 downto 0);
            LODEC:
            in std_logic_vector(2 downto 0);
            OPC:
            in std_logic_vector(4 downto 3);
            HIDB:
            in std_logic_vector(8 downto 7);
            HIDC:
            in std_logic_vector(13 downto 10);
            HI15,
            L5TF,
            NLCA,
            BRET,
            INDOP,
            INDXR,
            INDXW,
            NLDA,
            LOGDI,
            NMBC,
            JBC,
            NBEN,
            NSWA,
            NMCB:
            in std_logic
            );       
end component;
--*********************************************************************
--Signal definitions
--*********************************************************************
signal AB,AC,INDIRECT_OPS,MOVDAI,AI,AJ,AK,AM,AN: std_logic;
signal AU,AV,AW,AX,AY,MOVRDA,BA: std_logic;
signal ARITH_OPS, CARRY_OPS1, CARRY_OPS2, CARRY_OPS3: std_logic;
signal LODEC_4TOF, LDAA, NLJMP, NOP16, LNMULAB, LNDIVAB: std_logic;
signal NCPLB, NSETB, NSETC, NMOVCB, NMOVBC, NCLRB, NCLRC: std_logic;
signal NORLCN, NORLCB, NANLCN, NANLCB: std_logic;
signal LJBC, NCPLC, NMOVPC, NINCDP, NSWAPN: std_logic;