m3s007bo.vhd

来自「another 8051 core porocesssor vhdl sourc」· VHDL 代码 · 共 162 行

--*******************************************************************       --
--IMPORTANT NOTICE                                                          --
--================                                                          --
--Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  --
--This file and associated deliverables are the trade secrets,              --
--confidential information and copyrighted works of Mentor Graphics         --
--Corporation and its licensors and are subject to your license agreement   --
--with Mentor Graphics Corporation.                                         --
--                                                                          --
--Use of these deliverables for the purpose of making silicon from an IC    --
--design is limited to the terms and conditions of your license agreement   --
--with Mentor Graphics If you have further questions please contact Mentor  --
--Graphics Customer Support.                                                --
--                                                                          --
--This Mentor Graphics core (m8051 v1999.120) was extracted on              --
--workstation hostid _hostid_ Inventra                                      --
--Conditional jump test subblock for m8051
--Copyright Mentor Graphics Corporation and Licensors 1998. All rights reserved
--v1.008
--*********************************************************************
--@(#)m3s007bo.vhd	1.2 04/08/99 SCCS Version Control

--File	        :       m3s007bo.vhd
--Created on    :       8th October 1995
--Purpose       :       conditional jump test subblock for M8051
--Version       :       1.008
--Mod Date      :       2nd April 1998
--Mod History	:       1.008 _e suffix removed from entity names.
--                      1.007 STATDs 7-12 removed
--                      1.006 Sensivity List Revisions
--                      1.005 C_TRUE clocked at c2s4p1
--                      1.004-CTRU only clocked at end of CYC1
--                      1.003-changed CA inverted, CTRU delayed
--                      1.002-Calling file changed to m8051.vhd
--                      1.001(Original)
--
--
--*********************************************************************
--Hierarchy record      :
--Called by             :m8051.vhd
--Calls to              :None
--                      :
--                      :
--                      :
---------------------------------------------------
library IEEE;

use IEEE.std_logic_1164.all;
library WORK;

--*********************************************************************
--Entity Definition
--*********************************************************************

entity m3s007bo is
--*******************************************************************       --
--IMPORTANT NOTICE                                                          --
--================                                                          --
--Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  --
--This file and associated deliverables are the trade secrets,              --
--confidential information and copyrighted works of Mentor Graphics         --
--Corporation and its licensors and are subject to your license agreement   --
--with Mentor Graphics Corporation.                                         --
--                                                                          --
--Use of these deliverables for the purpose of making silicon from an IC    --
--design is limited to the terms and conditions of your license agreement   --
--with Mentor Graphics If you have further questions please contact Mentor  --
--Graphics Customer Support.                                                --
--                                                                          --
--This Mentor Graphics core (m8051 v1999.120) was extracted on              --
--workstation hostid _hostid_ Inventra                                      --
       port(C_TRUE:
            out std_logic;
            ALUDAT:
            in std_logic_vector(7 downto 0);
            OPC:
            in std_logic_vector(7 downto 4);
            PSWDAT:
            in std_logic_vector(7 downto 7);
            CYC:
            in std_logic_vector(2 downto 2);
            STATD:
            in std_logic_vector(3 downto 3);
            BBIT,
            DIV2CK,
            NX1,
            RST:
            in std_logic 
            );       
end m3s007bo;
--*********************************************************************
--Architecture definition
--*********************************************************************
architecture m3s007bo_rtl of m3s007bo is
--*********************************************************************

--*********************************************************************
--Signal definitions
--*********************************************************************
signal AA,CA,TMPCTRU:std_logic; 
--*********************************************************************
begin
--*********************************************************************
--Process Definitions
--*********************************************************************
accumulator_zero:process(ALUDAT)
-- test for zero in the accumulator via ALU bus
begin
   AA <= ALUDAT(0) or ALUDAT(1) or ALUDAT(2) or ALUDAT(3) or ALUDAT(4)
         or ALUDAT(5) or ALUDAT(6) or ALUDAT(7);
end process accumulator_zero;
--*********************************************************************
misc3:process(OPC,PSWDAT,BBIT,AA)
begin
  case OPC(6 downto 4) is
      when "000" => CA <= '1';
      when "001" => CA <= BBIT;
      when "010" => CA <= BBIT;
      when "011" => CA <= not BBIT;
      when "100" => CA <= PSWDAT(7);
      when "101" => CA <= not PSWDAT(7);
      when "110" => CA <= not AA;
      when "111" => CA <= AA;
      when others => CA <= 'X';
  end case;
end process misc3;
--*********************************************************************
misc4:process(OPC, AA, CA)
begin
  case OPC(7) is
      when '0' => TMPCTRU <= CA;
      when '1' => TMPCTRU <= AA;
      when others => TMPCTRU<= 'X';
  end case;
end process misc4;
--*********************************************************************
ctruout:process(NX1,RST)
-- Updates condition at the beginning of c2s4p1.  This output is used by
-- module m3s010bo at c2s5p1 and module m3s008 at c2s5p2 for jbc writes.
begin
    if RST ='1' then
       C_TRUE <= '0';
    elsif NX1'event and NX1 ='1' then
       if (CYC(2) and STATD(3) and not DIV2CK) ='1' then
           C_TRUE <= TMPCTRU;
       end if;
     end if;
end process ctruout;
--*********************************************************************
end m3s007bo_rtl;
--*********************************************************************