m3s018bo.vhd

来自「another 8051 core porocesssor vhdl sourc」· VHDL 代码 · 共 516 行 · 第 1/2 页

--*******************************************************************       --
--IMPORTANT NOTICE                                                          --
--================                                                          --
--Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  --
--This file and associated deliverables are the trade secrets,              --
--confidential information and copyrighted works of Mentor Graphics         --
--Corporation and its licensors and are subject to your license agreement   --
--with Mentor Graphics Corporation.                                         --
--                                                                          --
--Use of these deliverables for the purpose of making silicon from an IC    --
--design is limited to the terms and conditions of your license agreement   --
--with Mentor Graphics If you have further questions please contact Mentor  --
--Graphics Customer Support.                                                --
--                                                                          --
--This Mentor Graphics core (m8051 v1999.120) was extracted on              --
--workstation hostid _hostid_ Inventra                                      --
--Port Controller and Registers for M8051
--Copyright Mentor Graphics Corporation and Licensors 1998. All Rights Reserved.
--v1.011
--*********************************************************************
--@(#)m3s018bo.vhd	1.2 04/08/99 SCCS Version Control

--File	        :       m3s018bo.vhd
--Created on    :       17th Nov 1995
--Purpose       :       Port Control for M8051
--Version       :       1.011
--Mod Date      :       2nd April 1998
--Mod History	:       1.011 Port 2 output drive enable delay register
--                            modified to update unconditionally at the end
--                            of phase two.
--                            _e suffix removed from entity names.
--                      1.010 Port 0 output MUX controls re-written.
--                            Redundant signals removed.
--                      1.009 Name changes and sensitivity list
--                            revisions.
--                            Program address bus revisions.
--                      1.008 ECN 878: revised SFR writeback time.
--                            SFR write time moved to end of S6P2 and
--                            redundant SFR relay flip-flops deleted.
--                            No external timing change results.
--                            EXT_PROG_EN moved to m3s010bo.
--                      1.007 Port initialisation during reset
--                      1.006 Idle Mode Power Saving
--                      1.005 Change for reset compatibility and
--                            OPH and OPL changed to DPH and DPL
--                            ECN 865 Fix for external idle mode;
--                      1.004 Fix to match dummy address fetches
--                      1.003 ECN 837 Fix for movc high byte 
--                      1.002 Calling file name changed to m8051.vhd
--                      1.001 Original
--
--
--*********************************************************************
--Hierarchy record      :
--Called by             :m8051.vhd
--                      :
--                      :
--Calls to              :None
--                      :
--*********************************************************************
library IEEE;

use IEEE.std_logic_1164.all;
library WORK;

--*********************************************************************
--Entity Definition
--*********************************************************************

entity m3s018bo is 
--*******************************************************************       --
--IMPORTANT NOTICE                                                          --
--================                                                          --
--Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  --
--This file and associated deliverables are the trade secrets,              --
--confidential information and copyrighted works of Mentor Graphics         --
--Corporation and its licensors and are subject to your license agreement   --
--with Mentor Graphics Corporation.                                         --
--                                                                          --
--Use of these deliverables for the purpose of making silicon from an IC    --
--design is limited to the terms and conditions of your license agreement   --
--with Mentor Graphics If you have further questions please contact Mentor  --
--Graphics Customer Support.                                                --
--                                                                          --
--This Mentor Graphics core (m8051 v1999.120) was extracted on              --
--workstation hostid _hostid_ Inventra                                      --
       port(ALE,
            NPSEN,
            MOEI,
            EXPMEM:
            out std_logic;
            OAI,
            OB,
            OC,
            OD,
            AE,
            BE,
            CE,
            DE,
            PORTA,
            PORTB,
            PORTC,
            PORTD:
            out std_logic_vector(7 downto 0);
            PROGRAM_ADDR:
            in std_logic_vector(15 downto 0);
            AI,
            BI,
            CI,
            DI,
            RAMDI,
            DPL,
            DPH,
            ACCDAT,
            FA:
            in std_logic_vector(7 downto 0);
            STATD:
            in std_logic_vector(6 downto 1);
            MOVX:
            in std_logic_vector(4 downto 0);
            SFRW:
            in std_logic_vector(3 downto 0);
            CYC:
            in std_logic_vector(2 downto 1);
            PCON:
            in std_logic_vector(0 downto 0);
            XROM,
            EXT_PROG_EN,
            NEA,
            RXDO,
            TXDO,
            RMW,
            DIV2CK,
            NX1,
            NX2,
            CLEAR,
            RST,
            DLMR:
            in std_logic
            );
end m3s018bo;
--*********************************************************************
--Architecture definition
--*********************************************************************
architecture m3s018bo_rtl of m3s018bo is
--*********************************************************************


--*********************************************************************
--signal definition
--*********************************************************************
signal AA:std_logic;
signal L_EXPMEM,POPMEN,PODMEN,P0DADD,AEEN,EXTDAT,IDLE:std_logic;
signal QALE,NQEN,NRD,NWR,SELC, EXTEND_MOVX:std_logic;
signal PORT1_DEL, LOCALE, PORT2_DEL, PORT3_DEL:std_logic_vector(7 downto 0);
signal PORT0_SFR, PORT1_SFR, PORT2_SFR, PORT3_SFR: std_logic_vector(7 downto 0);
signal L_OC, L_OD:std_logic_vector(7 downto 0);
signal LAI_IN, LBI_IN, LCI_IN, LDI_IN:std_logic_vector(7 downto 0);
signal SELA:std_logic_vector(2 downto 0);
--*********************************************************************
begin
--*********************************************************************
--Process Definitions 
--*********************************************************************
misc1:process(STATD, MOVX, CYC)
begin
    AA <= STATD(3) or (STATD(6) and not(MOVX(0) and CYC(2)));
end process misc1;
--*********************************************************************
misc2:process(PODMEN, POPMEN, DLMR)
begin
    AEEN <= PODMEN or POPMEN or DLMR;
end process misc2;
--*********************************************************************
misc4:process(NX2,RST)
begin
    if RST = '1' then
       L_EXPMEM <= '0';
    elsif NX2'event and NX2 = '1' then
       if DIV2CK = '1' then
          L_EXPMEM <= EXT_PROG_EN;
       end if;
    end if;
end process misc4;
--*********************************************************************
setale:process(NX2,RST)
-- ALE runs continously regardless of whether program memory read is
-- internal or external.  Ale is only suspended by MOVX instructions.
begin
    if RST = '1' then
       QALE <= '1';
    elsif NX2'event and NX2 ='1' then  
       if DIV2CK ='1' then 
           QALE <= STATD(4) or (STATD(1) and not(MOVX(0) and CYC(2))) or (CLEAR and not STATD(5));
       end if;
    end if;    
end process setale;
--*********************************************************************
setpopmen:process(NX2)
begin
    if NX2'event and NX2 = '1' then
       if DIV2CK ='0' then
           POPMEN <= (XROM or not NEA) and ((STATD(1) and not CLEAR and
                      not(MOVX(0) and CYC(2)))
                     or (STATD(4) and not(MOVX(0) and CYC(1)))) and
                     not RST;
       end if ;
     end if;
end process setpopmen;
--*********************************************************************
set_port_sfrs:process(NX2, RST)
-- set port SFRs at end of S6P2.
-- Port 0 SFR is set to ones by certain external memory operations.
begin
   if RST = '1' then
      PORT0_SFR <= "11111111";
      PORT1_SFR <= "11111111";
      PORT2_SFR <= "11111111";
      PORT3_SFR <= "11111111";
   elsif NX2'event and NX2 = '1' then
      if DIV2CK ='0' then
         if (((EXT_PROG_EN or MOVX(0)) and AA) ='1') then
            PORT0_SFR <= "11111111";
         elsif SFRW(0) ='1' then PORT0_SFR <= RAMDI;
         end if;
         if SFRW(1) ='1' then PORT1_SFR <= RAMDI;
         end if;
         if SFRW(2) ='1' then PORT2_SFR <= RAMDI;
         end if;
         if SFRW(3) ='1' then PORT3_SFR <= RAMDI;
         end if;
      end if; -- not DIV2CK
   end if; -- NX2 event
end process set_port_sfrs;      
--********************************************************************* 
muxlocale:process(DPH,PROGRAM_ADDR,EXTDAT)
begin
   case EXTDAT is
       when '0' => LOCALE <= PROGRAM_ADDR(15 downto 8);
       when '1' => LOCALE <= DPH;
       when others => LOCALE <= "XXXXXXXX";
    end case;
end process muxlocale;
--*********************************************************************
setextdat:process(NX2)
begin
    if NX2'event and NX2 = '1' then
       if CLEAR = '1' then
             EXTDAT <= '0';
       elsif DIV2CK = '0' then
          if ((STATD(4) and CYC(1) and MOVX(0)) ='1') then
             EXTDAT <= '1';
          elsif ((STATD(4) and CYC(2)) ='1') then
             EXTDAT <= '0';
          end if;
       end if;
    end if;
end process setextdat;