m3s027bo.vhd

来自「another 8051 core porocesssor vhdl sourc」· VHDL 代码 · 共 122 行

--*******************************************************************       --
--IMPORTANT NOTICE                                                          --
--================                                                          --
--Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  --
--This file and associated deliverables are the trade secrets,              --
--confidential information and copyrighted works of Mentor Graphics         --
--Corporation and its licensors and are subject to your license agreement   --
--with Mentor Graphics Corporation.                                         --
--                                                                          --
--Use of these deliverables for the purpose of making silicon from an IC    --
--design is limited to the terms and conditions of your license agreement   --
--with Mentor Graphics If you have further questions please contact Mentor  --
--Graphics Customer Support.                                                --
--                                                                          --
--This Mentor Graphics core (m8051 v1999.120) was extracted on              --
--workstation hostid _hostid_ Inventra                                      --
--4 Bit sum sub-block for m8051
--Copyright Mentor Graphics Corporation and Licensors 1998.  All rights reserved
--v1.002
--*********************************************************************
--@(#)m3s027bo.vhd	1.2 04/08/99 SCCS Version Control

--File	        :       m3s027bo.vhd
--Created on    :       12th October 1995
--Purpose       :       4 Bit sum sub-block for m8051
--Version       :       1.002
--Mod Date      :       2nd April 1998
--Mod History	:       1.002 _e suffix removed from entity names.
--
--
--
--*********************************************************************
--Hierarchy record      :
--Called by             :m3s011bo.vhd
--Calls to              :None
--                      :
--                      :
--                      :
---------------------------------------------------
library IEEE;

use IEEE.std_logic_1164.all;
library WORK;

--*********************************************************************
--Entity Definition
--*********************************************************************

entity m3s027bo is
--*******************************************************************       --
--IMPORTANT NOTICE                                                          --
--================                                                          --
--Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  --
--This file and associated deliverables are the trade secrets,              --
--confidential information and copyrighted works of Mentor Graphics         --
--Corporation and its licensors and are subject to your license agreement   --
--with Mentor Graphics Corporation.                                         --
--                                                                          --
--Use of these deliverables for the purpose of making silicon from an IC    --
--design is limited to the terms and conditions of your license agreement   --
--with Mentor Graphics If you have further questions please contact Mentor  --
--Graphics Customer Support.                                                --
--                                                                          --
--This Mentor Graphics core (m8051 v1999.120) was extracted on              --
--workstation hostid _hostid_ Inventra                                      --
       port(SUM:
            out std_logic_vector(3 downto 0);
            NG,
            P:
            in std_logic_vector(3 downto 0);
            NCI:
            in std_logic 
            );       
end m3s027bo;
--*********************************************************************
--Architecture definition
--*********************************************************************
architecture m3s027bo_rtl of m3s027bo is
--*********************************************************************

--*********************************************************************
--Signal definitions
--*********************************************************************
signal AA,AB,AC,AD,AE,AF,AG,AH,AI,AJ:std_logic;
signal BA,BB,BC:std_logic;
--*********************************************************************
begin
--*********************************************************************
--Process Definitions
--*********************************************************************
misc1:process(P,NG,NCI)
begin
   AA <= P(3) and NG(3);
   AB <= (not P(1)) and NG(2);
   AC <= (not P(0)) and NG(2) and NG(1);
   AD <= NCI and NG(2) and NG(1) and NG(0);
   AE <= P(2) and NG(2);
   AF <= (not P(0)) and NG(1);
   AG <= NCI and NG(1) and NG(0);
   AH <= P(1) and NG(1);
   AI <= NCI and NG(0);
   AJ <= P(0) and NG(0);
end process misc1;
--*********************************************************************
misc2:process(P,AB,AC,AD,AF,AG,AI)
begin
   BA <= (not P(2)) or AB or AC or AD;
   BB <= (not P(1)) or AF or AG;
   BC <= (not P(0)) or AI;
end process misc2;
--*********************************************************************
sumout:process(AA,AE,AH,AJ,BA,BB,BC,NCI)
begin
   SUM(0) <= (not AJ) xor NCI;
   SUM(1) <= (not AH) xor BC;
   SUM(2) <= (not AE) xor BB;
   SUM(3) <= (not AA) xor BA;
end process sumout;
--*********************************************************************
end m3s027bo_rtl;
--*********************************************************************