m3s003bo.vhd

来自「another 8051 core porocesssor vhdl sourc」· VHDL 代码 · 共 446 行 · 第 1/2 页

--*******************************************************************       --
--IMPORTANT NOTICE                                                          --
--================                                                          --
--Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  --
--This file and associated deliverables are the trade secrets,              --
--confidential information and copyrighted works of Mentor Graphics         --
--Corporation and its licensors and are subject to your license agreement   --
--with Mentor Graphics Corporation.                                         --
--                                                                          --
--Use of these deliverables for the purpose of making silicon from an IC    --
--design is limited to the terms and conditions of your license agreement   --
--with Mentor Graphics If you have further questions please contact Mentor  --
--Graphics Customer Support.                                                --
--                                                                          --
--This Mentor Graphics core (m8051 v1999.120) was extracted on              --
--workstation hostid _hostid_ Inventra                                      --
-- 8-Bit Arithmetic Logic Unit for m8051
--Copyright Mentor Graphics Corporation and Licensors 1998. All Rights Reserved.
--v1.006
--*********************************************************************
--@(#)m3s003bo.vhd	1.2 04/08/99 SCCS Version Control

--File	        :       m3s003bo.vhd
--Created on    :       14th October 1995
--Purpose       :       2 x 4 bit ALU,with look ahead carry for m8051
--Version       :       1.006
--Mod Date      :       2nd April 1998
--Mod History	:       1.006 _e suffix removed from entity names.
--                      1.005 Look-ahead carry restored to design.
--                      1.004 Sensitivity list revisions, redundant
--                            decode removed.
--                      1.003-ECN 857-CARI in sensitivity list
--                      1.002-Calling file name changed to m8051.vhd
--                      1.001(Original)
--
--
--*********************************************************************
--Hierarchy record      :
--Called by             :m8051.vhd
--Calls to              :m3s002bo.vhd
--                      :
--                      :
--                      :
--*********************************************************************
library IEEE;

use IEEE.std_logic_1164.all;
library WORK;
use WORK.all;

--*********************************************************************
--Entity Definition
--*********************************************************************

entity m3s003bo is
--*******************************************************************       --
--IMPORTANT NOTICE                                                          --
--================                                                          --
--Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  --
--This file and associated deliverables are the trade secrets,              --
--confidential information and copyrighted works of Mentor Graphics         --
--Corporation and its licensors and are subject to your license agreement   --
--with Mentor Graphics Corporation.                                         --
--                                                                          --
--Use of these deliverables for the purpose of making silicon from an IC    --
--design is limited to the terms and conditions of your license agreement   --
--with Mentor Graphics If you have further questions please contact Mentor  --
--Graphics Customer Support.                                                --
--                                                                          --
--This Mentor Graphics core (m8051 v1999.120) was extracted on              --
--workstation hostid _hostid_ Inventra                                      --
       port(ALUDAT,
            CPRDDM:
            out std_logic_vector(7 downto 0);
            CO,
            ACO,
            OV,
            BBIT:
            out std_logic;
            ACLDAT:
            in std_logic_vector(9 downto 0);         
            TMPDAT:
            in std_logic_vector(7 downto 0);
            ALUC:
            in std_logic_vector(17 downto 0);--bit 13 not used
            ACCDAT:
            in std_logic_vector(7 downto 7);
            BIT_POSN:
            in std_logic_vector(2 downto 0);
            NMULAB,
            NDIVAB,
            DAA,
            ACC0:
            in std_logic
            );       
end m3s003bo;
--*********************************************************************
--Architecture definition
--*********************************************************************
architecture m3s003bo_rtl of m3s003bo is
--*********************************************************************
--*********************************************************************
--Component Definitions
--*********************************************************************
-- ALU primitive components: bit slice and 4-bit carry look-ahead units

component m3s002bo
       port(P,
            CO:   out std_logic;
            ALUC: in  std_logic_vector(5 downto 0);
            A,
            B:    in std_logic 
            ); 
end component;

component m3s041bo
       port(S:    out std_logic_vector(3 downto 0);
            P:    in  std_logic_vector(3 downto 0);
            G:    in  std_logic_vector(2 downto 0);
            C_IN: in  std_logic;
            C_EN: in  std_logic 
            );
end component;

--*********************************************************************
--Signal definitions
--*********************************************************************
signal QCI,CMUX,CBEN,CAM,CARI,LBBIT:std_logic;
signal AA,AB,AC,AD,AE,AF,PROP_LO,AH,AR,AS,AT,AU,AV,AW:std_logic;
signal AAA,AAB,AAC,AAD,AAE,AAF:std_logic;
signal GEN_LO,BB,BC,BD,BE,BF,BG,CA,CB,CC,CD,CE,CF,CG,CH,DA,DB,DC:std_logic;
signal EJ, EK: std_logic;
signal LOCALA,LOCALB,LOCALC,LOCALD,LOCALE,LOCALF:std_logic;
signal ALU_PROP, ALU_GEN, ALU_SUM: std_logic_vector(7 downto 0);
signal ALUP, LDATAA: std_logic_vector(7 downto 0);
signal muxvect1:std_logic_vector(1 downto 0);
--*********************************************************************
--Port Mapping
--*********************************************************************
begin
--*********************************************************************
U1:m3s002bo
 port map(
          P => ALU_PROP(0),
          CO => ALU_GEN(0),
          ALUC => ALUC(5 downto 0),
          A => ACLDAT(0),
          B => TMPDAT(0)
         );
--*********************************************************************
U2:m3s002bo
 port map(
          P => ALU_PROP(1),
          CO => ALU_GEN(1),
          ALUC => ALUC(5 downto 0),
          A => ACLDAT(1),
          B => TMPDAT(1)
         );
--*********************************************************************
U3:m3s002bo
 port map(
          P => ALU_PROP(2),
          CO => ALU_GEN(2),
          ALUC => ALUC(5 downto 0),
          A => ACLDAT(2),
          B => TMPDAT(2)
         );
--*********************************************************************
U4:m3s002bo
 port map(
          P => ALU_PROP(3),
          CO => ALU_GEN(3),
          ALUC => ALUC(5 downto 0),
          A => ACLDAT(3),
          B => TMPDAT(3)
         );
--*********************************************************************
U5:m3s002bo
 port map(
          P => ALU_PROP(4),
          CO => ALU_GEN(4),
          ALUC => ALUC(5 downto 0),
          A => ACLDAT(4),
          B => TMPDAT(4)
         );
--*********************************************************************
U6:m3s002bo
 port map(
          P => ALU_PROP(5),
          CO => ALU_GEN(5),
          ALUC => ALUC(5 downto 0),
          A => ACLDAT(5),
          B => TMPDAT(5)
         );
--*********************************************************************
U7:m3s002bo
 port map(
          P => ALU_PROP(6),
          CO => ALU_GEN(6),
          ALUC => ALUC(5 downto 0),
          A => ACLDAT(6),
          B => TMPDAT(6)
         );
--*********************************************************************
U8:m3s002bo
 port map(
          P => ALU_PROP(7),
          CO => ALU_GEN(7),
          ALUC => ALUC(5 downto 0),
          A => ACLDAT(7),
          B => TMPDAT(7)
         );
--*********************************************************************
U9:m3s041bo
 port map( 
          S => ALU_SUM(3 downto 0),
          P => ALU_PROP(3 downto 0),
          G => ALU_GEN(2 downto 0),
          C_IN => QCI,
          C_EN => CBEN
         );
--*********************************************************************
U10:m3s041bo