m3s030bo.vhd

来自「another 8051 core porocesssor vhdl sourc」· VHDL 代码 · 共 125 行

--*******************************************************************       --
--IMPORTANT NOTICE                                                          --
--================                                                          --
--Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  --
--This file and associated deliverables are the trade secrets,              --
--confidential information and copyrighted works of Mentor Graphics         --
--Corporation and its licensors and are subject to your license agreement   --
--with Mentor Graphics Corporation.                                         --
--                                                                          --
--Use of these deliverables for the purpose of making silicon from an IC    --
--design is limited to the terms and conditions of your license agreement   --
--with Mentor Graphics If you have further questions please contact Mentor  --
--Graphics Customer Support.                                                --
--                                                                          --
--This Mentor Graphics core (m8051 v1999.120) was extracted on              --
--workstation hostid _hostid_ Inventra                                      --
--TX shift register for UART of M8051
--Copyright Mentor Graphics Corporation and Licensors 1998.  All rights reserved
--v1.002
--*********************************************************************
--@(#)m3s030bo.vhd	1.2 04/08/99 SCCS Version Control

--File	        :       m3s030bo.vhd
--Created on    :       14th Dec 1995
--Purpose       :       TX shift register for UART of M8051
--Version       :       1.002
--Mod Date      :       2nd April 1998
--Mod History	:       1.002 _e suffix removed from entity names.
--
--
--
--
--*********************************************************************
--Hierarchy record      :
--Called by             :m3s028bo.vhd
--                      :
--                      :
--Calls to              :None
--*********************************************************************
library IEEE;

use IEEE.std_logic_1164.all;
library WORK;

--*********************************************************************
--Entity Definition
--*********************************************************************

entity m3s030bo is 
--*******************************************************************       --
--IMPORTANT NOTICE                                                          --
--================                                                          --
--Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  --
--This file and associated deliverables are the trade secrets,              --
--confidential information and copyrighted works of Mentor Graphics         --
--Corporation and its licensors and are subject to your license agreement   --
--with Mentor Graphics Corporation.                                         --
--                                                                          --
--Use of these deliverables for the purpose of making silicon from an IC    --
--design is limited to the terms and conditions of your license agreement   --
--with Mentor Graphics If you have further questions please contact Mentor  --
--Graphics Customer Support.                                                --
--                                                                          --
--This Mentor Graphics core (m8051 v1999.120) was extracted on              --
--workstation hostid _hostid_ Inventra                                      --
       port(SOUT,
            QLOW:
            out std_logic;
            NEWDATA,
            CLEAR,
            TSHIFT_EN,
            TSHIFT_IN,
            NX1:
            in std_logic;
            RAMDI:
            in std_logic_vector(7 downto 0)
            );
end m3s030bo;
--*********************************************************************
--Architecture definition
--*********************************************************************
architecture m3s030bo_rtl of m3s030bo is
--*********************************************************************
--*********************************************************************
--signal definition
--*********************************************************************
signal DAT:std_logic_vector(7 downto 0);
--*********************************************************************
begin
--*********************************************************************
-- Process Definitions
--*********************************************************************
mrshifter:process(NX1)
begin
    if NX1'event and NX1 ='1' then
        if CLEAR ='1' then
            DAT <= "00000000";
        elsif TSHIFT_EN = '1' then
           if NEWDATA = '1' then
               DAT <= RAMDI;
           else
               DAT(0) <= DAT(1);
               DAT(1) <= DAT(2);
               DAT(2) <= DAT(3);
               DAT(3) <= DAT(4);
               DAT(4) <= DAT(5);
               DAT(5) <= DAT(6);
               DAT(6) <= DAT(7);
               DAT(7) <= TSHIFT_IN;
           end if;
        end if;
    end if;
end process mrshifter;
--*********************************************************************
set_outs:process(DAT)
begin
   SOUT <= DAT(0);
   QLOW <= not(DAT(7) or DAT(6) or DAT(5) or DAT(4) or DAT(3) or DAT(2));
end process set_outs;
--*********************************************************************
end m3s030bo_rtl;
--*********************************************************************