m3s028bo.vhd

来自「another 8051 core porocesssor vhdl sourc」· VHDL 代码 · 共 812 行 · 第 1/2 页

--*******************************************************************       --
--IMPORTANT NOTICE                                                          --
--================                                                          --
--Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  --
--This file and associated deliverables are the trade secrets,              --
--confidential information and copyrighted works of Mentor Graphics         --
--Corporation and its licensors and are subject to your license agreement   --
--with Mentor Graphics Corporation.                                         --
--                                                                          --
--Use of these deliverables for the purpose of making silicon from an IC    --
--design is limited to the terms and conditions of your license agreement   --
--with Mentor Graphics If you have further questions please contact Mentor  --
--Graphics Customer Support.                                                --
--                                                                          --
--This Mentor Graphics core (m8051 v1999.120) was extracted on              --
--workstation hostid _hostid_ Inventra                                      --
--UART for M8051
--Copyright Mentor Graphics Corporation and Licensors 1999. All rights reserved.
--v1.103
--*********************************************************************
--@(#)m3s028bo.vhd	1.2 04/08/99 SCCS Version Control
--File	        :       m3s028bo.vhd
--Created on    :       15th Dec 1995
--Purpose       :       UART for M8051
--Version       :       1.103
--Mod Date      :       25th March 1999
--Mod History	:       1.103 ECN 1226 - Fix to UART receiver in mode 0
--                            ECN 1140 - RI bit in modes 2 & 3 dependency on SM2
--                      1.102 ECN 1185 - SCON.4 now disables reception at any
--                            stage
--                      1.101 _e suffix removed from entity names.
--                      1.100 ECN1053 - Serial receive mode 0 fixed
--			1.009 Redundant port removed.
--                      1.008 Rename divider carry outputs for Verilog
--                            compatibility.
--                      1.007 UART sampling time and latency fixes.
--                            Sensitivity list revisions.
--                      1.006 Port initialisation during reset
--                      1.005 Idle Mode Power Saving
--			1.004 ECN 812-9 bit mode
--                      1.003-Calling file changed to m8051.vhd
--                            LTCI bus added for verilog conversion, 
--                            no circuit change
--                      1.002-ECNs 742,743
--                      1.001(Original)
--
--
--
--*********************************************************************
--Hierarchy record      :
--Called by             :m8051.vhd
--                      :
--                      :
--Calls to              :m3s029bo.vhd
--                      :m3s030bo.vhd
--                      :m3s031bo.vhd
--*********************************************************************
library IEEE;

use IEEE.std_logic_1164.all;
library WORK;

--*********************************************************************
--Entity Definition
--*********************************************************************

entity m3s028bo is 
--*******************************************************************       --
--IMPORTANT NOTICE                                                          --
--================                                                          --
--Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  --
--This file and associated deliverables are the trade secrets,              --
--confidential information and copyrighted works of Mentor Graphics         --
--Corporation and its licensors and are subject to your license agreement   --
--with Mentor Graphics Corporation.                                         --
--                                                                          --
--Use of these deliverables for the purpose of making silicon from an IC    --
--design is limited to the terms and conditions of your license agreement   --
--with Mentor Graphics If you have further questions please contact Mentor  --
--Graphics Customer Support.                                                --
--                                                                          --
--This Mentor Graphics core (m8051 v1999.120) was extracted on              --
--workstation hostid _hostid_ Inventra                                      --
       port(
            SCON,
            SBUF:
            out std_logic_vector(7 downto 0);
            RITI,
            RXDO,
            TXDO:
            out std_logic;
            DI:
            in std_logic_vector(0 downto 0);
            RAMDI:
            in std_logic_vector(7 downto 0);
            PCON:
            in std_logic_vector(7 downto 7);
            SFRW:
            in std_logic_vector(11 downto 10);
            LOV1,
            S_EN,
            T_EN,
            STATE12,
            DIV2CK1,
            NX1,
            NX2,
            CLEAR:
            in std_logic
            );
end m3s028bo;
--*********************************************************************
--Architecture definition
--*********************************************************************
architecture m3s028bo_rtl of m3s028bo is
--*********************************************************************
--*********************************************************************
-- Component Definitions
--*********************************************************************
--1 up bit counter(sync clear)
component m3s029bo
       port(CO,
            Q:
            out std_logic;
            CI,
            CLEAR,
            COUNT_EN,
            NX1:
            in std_logic
            );
end component;
--*********************************************************************
--TX shift reg
component m3s030bo
       port(SOUT,
            QLOW:
            out std_logic;
            CLEAR,
            NEWDATA,
            TSHIFT_EN,
            TSHIFT_IN,
            NX1:
            in std_logic;
            RAMDI:
            in std_logic_vector(7 downto 0)
            );
end component;
--*********************************************************************
--RX shift reg
component m3s031bo
       port(FRM:
            out std_logic_vector(7 downto 0);
            D0,
            LORCV,
            RSHIFT_EN,
            RSHIFT_IN,
            NX1:
            in std_logic
            );
end component;
--*********************************************************************
--signal definition
--*********************************************************************
signal COUNT_EN,TSHIFT_EN,TSHIFT_IN,SOUT:std_logic;
signal RSHIFT_EN,RSHIFT_IN,QLOW,NEWDATA:std_logic;
signal AE,AF,BLOCK_SBUF_LD,AH:std_logic;
signal TXLASTBIT,TXEND,TISET,RISET:std_logic;
signal DCKM,CKMASK,CLEAR16C_RX,CLEAR16C_TX,MODE0,DIVTWO,MAJOUT,TSEND:std_logic;
signal D0,Q1,Q3,Q5,Q6,END_DATA:std_logic;
signal TXSTOPBIT,FLST,FSREJ,RXC7,RXC8,RXC9,TXCLK,SETTXCLK:std_logic;
signal RSTQ1,RX_EN,TX_EN,DATAEN,RX_DIN,CLR_RCV,DELCLRRCV:std_logic;
signal RCV,DELRCV,BITIN,SWREC,LORCV,SELRB8,RST16C,DELRST16C,DELCNT:std_logic;
signal MODE0_IN,MAJQ1,MAJQ2,LRITI:std_logic;
signal TCI, RCI, TX_DIV, RX_DIV:std_logic_vector(3 downto 0);
signal LTCI, LRCI:std_logic_vector(3 downto 1);
signal FRM:std_logic_vector(7 downto 0);
signal L_SCON:std_logic_vector(7 downto 3);
signal LL_SCON:std_logic_vector(2 downto 0);
--*********************************************************************
--*********************************************************************
--port mapping
--*********************************************************************
begin
--*********************************************************************
U1:m3s029bo --MSBit TX generator
  port map(
           CO => open,
           Q => TX_DIV(3),
           CI => TCI(3),
           CLEAR => CLEAR16C_TX,
           COUNT_EN => COUNT_EN,
           NX1 => NX1
           );
--*********************************************************************
U2:m3s029bo -- TX generator
  port map(
           CO => LTCI(3),
           Q => TX_DIV(2),
           CI => TCI(2),
           CLEAR => CLEAR16C_TX,
           COUNT_EN => COUNT_EN,
           NX1 => NX1
           );
--*********************************************************************
U3:m3s029bo -- TX generator
  port map(
           CO => LTCI(2),
           Q => TX_DIV(1),
           CI => TCI(1),
           CLEAR => CLEAR16C_TX,
           COUNT_EN => COUNT_EN,
           NX1 => NX1
           );
--*********************************************************************
U4:m3s029bo --LSBit TX generator
  port map(
           CO => LTCI(1),
           Q => TX_DIV(0),
           CI => TCI(0),
           CLEAR => CLEAR16C_TX,
           COUNT_EN => COUNT_EN,
           NX1 => NX1
           );
--*********************************************************************
U5:m3s029bo --MSBit RX generator
  port map(
           CO => open,
           Q => RX_DIV(3),
           CI => RCI(3),
           CLEAR => CLEAR16C_RX,
           COUNT_EN => COUNT_EN,
           NX1 => NX1
           );
--*********************************************************************
U6:m3s029bo -- RX generator
  port map(
           CO => LRCI(3),
           Q => RX_DIV(2),
           CI => RCI(2),
           CLEAR => CLEAR16C_RX,
           COUNT_EN => COUNT_EN,
           NX1 => NX1
           );
--*********************************************************************
U7:m3s029bo --RX generator
  port map(
           CO => LRCI(2),
           Q => RX_DIV(1),
           CI => RCI(1),
           CLEAR => CLEAR16C_RX,
           COUNT_EN => COUNT_EN,
           NX1 => NX1
           );
--*********************************************************************
U8:m3s029bo --LSBit RX generator
  port map(
           CO => LRCI(1),
           Q => RX_DIV(0),
           CI => TCI(0),
           CLEAR => CLEAR16C_RX,
           COUNT_EN => COUNT_EN,
           NX1 => NX1
           );
--*********************************************************************
U9:m3s030bo --TX Buffer
  port map(
           SOUT => SOUT,
           QLOW => QLOW,
           NEWDATA => NEWDATA,
           CLEAR => CLEAR,
           TSHIFT_EN => TSHIFT_EN,
           TSHIFT_IN => TSHIFT_IN,
           NX1 => NX1,
           RAMDI => RAMDI
           );
--*********************************************************************
U10:m3s031bo --RX Buffer
  port map(
           FRM => FRM,
           D0 => D0,
           LORCV => LORCV,
           RSHIFT_EN => RSHIFT_EN,
           RSHIFT_IN => RSHIFT_IN,
           NX1 => NX1
           );
--*********************************************************************
--Process Definitions 
--*********************************************************************
setsconhi:process(NX2)
begin
    if NX2'event and NX2 ='1' then
        if CLEAR ='1' then
            L_SCON(7 downto 3) <= "00000";
        else
           if SFRW(10) = '1' then
               L_SCON(7 downto 3) <= RAMDI(7 downto 3);        
           end if;
        end if;
    end if;
end process setsconhi;
--*********************************************************************
setsconlo:process(NX1)
begin
    if NX1'event and NX1 ='1' then
        if CLEAR ='1' then
            LL_SCON(2 downto 0) <= "000";
        else
           if SFRW(10) = '1' then
               LL_SCON(2) <= RAMDI(2);
           elsif (RISET and SELRB8)= '1' then
               if DELRCV = '0' then
                  if L_SCON(7) ='0' then
                      if (L_SCON(6) and not L_SCON(5)) = '1' then
                          LL_SCON(2) <= MAJOUT;
                      end if;
                  else
                      LL_SCON(2) <= BITIN;
                  end if;
               else
                  LL_SCON(2) <= MAJOUT;
               end if;         
           end if;
           if TISET = '1' then
               LL_SCON(1) <= '1';
           elsif SFRW(10) = '1' then
               LL_SCON(1) <= RAMDI(1);         
           end if;
           if RISET = '1' then
               LL_SCON(0) <= '1';
           elsif SFRW(10) = '1' then
               LL_SCON(0) <= RAMDI(0);         
           end if;
        end if;
    end if;
end process setsconlo;
--*********************************************************************
gen1:process(RAMDI,L_SCON,LL_SCON,SFRW,CLEAR,RST16C,DIVTWO,PCON,NEWDATA,TSHIFT_EN)
begin
   DCKM <= ((RAMDI(7) xor L_SCON(7)) or (RAMDI(7) xor L_SCON(7))) and SFRW(10);
   MODE0 <= not(L_SCON(6) or L_SCON(7));
   CLEAR16C_RX <= CLEAR or RST16C;
   CLEAR16C_TX <= CLEAR or (TSHIFT_EN and NEWDATA);
   TCI(0) <= DIVTWO or PCON(7);
end process gen1;
--*********************************************************************
gen2:process(TX_EN,DIV2CK1,DATAEN,SOUT,MODE0,TSEND,RCV,SFRW,TXCLK,TXLASTBIT,TXEND)
begin
   TSHIFT_EN <= (TX_EN and (not DIV2CK1) and DATAEN) or SFRW(11);
   RXDO <= SOUT or (not MODE0) or (not TSEND); 
   TXDO <= not((MODE0 and (not TXCLK) and (RCV or TSEND)) or ((not MODE0) and TSEND and (not TXLASTBIT) and not(DATAEN and SOUT)));
   D0 <= not MODE0;
   TISET <= (MODE0 and TXEND) or (TXLASTBIT and not MODE0);
end process gen2;
--*********************************************************************
gen3:process(RSTQ1,RCV,RX_DIN,L_SCON,MODE0)
begin
   RST16C <= (not RSTQ1) and (RCV or  not RX_DIN) and L_SCON(4) and not MODE0;
end process gen3;
--*********************************************************************
set_riti:process(NX1)
begin
   if NX1'event and NX1 ='1' then
       if CLEAR = '1' then
           LRITI <= '0';
       elsif MODE0 = '1' then
           LRITI <= LL_SCON(0) or LL_SCON(1);
       elsif (S_EN and DIV2CK1) = '1' then
           LRITI <= RISET or TISET or  LL_SCON(0) or LL_SCON(1);
       elsif (LL_SCON(0) or LL_SCON(1)) = '0' then
           LRITI <= '0';
       end if;
   end if;
end process set_riti;
--*********************************************************************
setdelrst:process(NX1)
begin
   if NX1'event and NX1 ='1' then
      if COUNT_EN = '1' then
         DELRST16C <= RST16C;
      end if;
   end if;
end process setdelrst;
--*********************************************************************
gen4:process(DELRCV, SWREC, RX_EN, DELRST16C, DIV2CK1, CLEAR, LORCV, CLR_RCV,
             L_SCON, END_DATA, BLOCK_SBUF_LD, MODE0)
begin
   RSHIFT_EN <=  ((DELRCV or not SWREC) and RX_EN and not DIV2CK1 and
                  (not CLR_RCV or not L_SCON(7))) 
                  or (DELRST16C and LORCV) or CLEAR;
   RISET <= END_DATA and (MODE0 or not BLOCK_SBUF_LD);
end process gen4;
--*********************************************************************
gen5:process(FSREJ,RCV,MODE0,MAJOUT,CLEAR)
begin
   FLST <= CLEAR or (MAJOUT and RCV and (not MODE0) and not FSREJ);
end process gen5;
--*********************************************************************
misc1:process(RX_DIV,CLEAR16C_RX,MAJOUT,L_SCON,LL_SCON)
begin
   AF <=  RX_DIV(3) or (not RX_DIV(2)) or RX_DIV(1) or RX_DIV(0) or CLEAR16C_RX;
   AE <= RX_DIV(3) or (not RX_DIV(2)) or RX_DIV(1) or (not RX_DIV(0)) or CLEAR16C_RX;
   AH <= RX_DIV(3) or (not RX_DIV(2)) or (not RX_DIV(1)) or RX_DIV(0) or CLEAR16C_RX;
   BLOCK_SBUF_LD <= ((not MAJOUT) and L_SCON(5)) or LL_SCON(0); 
end process misc1;
--*********************************************************************
countrxtx:process(L_SCON,CKMASK,DIV2CK1,LOV1)
begin