msim.scr

another 8051 core porocesssor vhdl source code

#!/bin/csh -f
# msim.scr - simulator script for Verilog simulation of M8051
# This script compiles and simulates the Verilog deliverable test bench

set SRC_DIR = "../rtl"
set TEST = "func1"
set CODE_DIR = "../../assembler/deliverable"
set REF_DIR  = "../../vhdl/sim"
set LIS_DIR = lis
set NET_DIR = "../gates/synop"
set RUNTIME = "742400 ns"

# Deal with command Line arguments
foreach OPTION ($argv)
  switch ($OPTION)
    case -g:
      set gates
      breaksw
    case -c:
      set ngui_mode
      breaksw
    default:
      echo "${0}: Unknown option ${OPTION}"
      exit 1
  endsw
end

# Create a listing repository if it does not already exist
if (!(-d ${LIS_DIR})) mkdir ${LIS_DIR}

# Re-create modelsim working directory
if (-e work) rm -r work
vlib work

if ($?gates) then
  # Compile the netlist
  vlog -nologo ${NET_DIR}/m8051.v
  set VSIM_OPTIONS = "-t ns -noglitch -L ver_lib -sdftyp /u2=${NET_DIR}/m8051.sdf"
  set TYPE = gate
else
  # Compile the core RTL modules into the library work.
  vlog ${SRC_DIR}/m3s001bo.v \
       ${SRC_DIR}/m3s002bo.v \
       ${SRC_DIR}/m3s005bo.v \
       ${SRC_DIR}/m3s006bo.v \
       ${SRC_DIR}/m3s007bo.v \
       ${SRC_DIR}/m3s009bo.v \
       ${SRC_DIR}/m3s013bo.v \
       ${SRC_DIR}/m3s014bo.v \
       ${SRC_DIR}/m3s018bo.v \
       ${SRC_DIR}/m3s019bo.v \
       ${SRC_DIR}/m3s022bo.v \
       ${SRC_DIR}/m3s023bo.v \
       ${SRC_DIR}/m3s024bo.v \
       ${SRC_DIR}/m3s025bo.v \
       ${SRC_DIR}/m3s027bo.v \
       ${SRC_DIR}/m3s029bo.v \
       ${SRC_DIR}/m3s030bo.v \
       ${SRC_DIR}/m3s031bo.v \
       ${SRC_DIR}/m3s032bo.v \
       ${SRC_DIR}/m3s033bo.v \
       ${SRC_DIR}/m3s034bo.v \
       ${SRC_DIR}/m3s035bo.v \
       ${SRC_DIR}/m3s039bo.v \
       ${SRC_DIR}/m3s040bo.v \
       ${SRC_DIR}/m3s041bo.v \
       ${SRC_DIR}/m3s003bo.v \
       ${SRC_DIR}/m3s004bo.v \
       ${SRC_DIR}/m3s008bo.v \
       ${SRC_DIR}/m3s011bo.v \
       ${SRC_DIR}/m3s016bo.v \
       ${SRC_DIR}/m3s020bo.v \
       ${SRC_DIR}/m3s028bo.v \
       ${SRC_DIR}/m3s010bo.v \
       ${SRC_DIR}/m3s015bo.v \
       ${SRC_DIR}/m8051.v

  set VSIM_OPTIONS = "-t ns"
  set TYPE = rtl
endif

# Compile the Testbench
vlog   io_cell.v \
       p0_io_cell.v \
       io_buffer.v \
       rom.v \
       ram.v \
       m8051_tb.v

# Link the assembler code
rm -f default_rom.rom
ln -s ${CODE_DIR}/${TEST}.rom default_rom.rom

# Run the simulation
if ($?ngui_mode) then
  vsim -c m8051_tb ${VSIM_OPTIONS} -do "run ${RUNTIME}; quit -f" | \
  tee ./msim_${TYPE}.log
else
  vsim m8051_tb ${VSIM_OPTIONS} -do "do wave.do; run ${RUNTIME}; quit -f" | \
  tee ./msim_${TYPE}.log
endif

# Correlate results
if (-e ${REF_DIR}/m8051uni.ref) then
   diff -i ${REF_DIR}/m8051uni.ref m8051uni.lis > m8051uni.rtl.diff
else
   echo Cannot read reference file ${REF_DIR}/m8051uni.ref
   exit(1)
endif
ls -l ${REF_DIR}/m8051uni.ref  m8051uni.lis m8051uni.rtl.diff