ram.v

another 8051 core porocesssor vhdl source code

//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
///////////////////////////////////////////////////////////////////////////////
// File                 :       ram.vhd
// Author               :       Ken Dennis
// Library              :       WORK
// Created on           :       July 2nd 1996
// Purpose              :       RAM Model
// Version              :       1.001
// Mod_Date             :       July 3rd 1996
// Mod_Hist             :   
///////////////////////////////////////////////////////////////////////////////
// Hierarchy record :
// called by:
// 
// calls to:
// none
///////////////////////////////////////////////////////////////////////////////
//Function of the entity : A model of the ROM has been constructed.
///////////////////////////////////////////////////////////////////////////////


module ram (data_in, data_out, address, nrawr, nrard, ncs);
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051 v1999.120) was extracted on              //
//workstation hostid _hostid_ Inventra                                      //
//
// The RAM model opens a specified Intel style Hex files and loads its self
// after load is finished it acts just like a RAM.
// 

   input [7:0] data_in;
   output [7:0] data_out;
   input [7:0] address;
   input  nrawr;
   input  nrard;
   input  ncs;


reg [7:0] ram_data [0:255];  // 4K Word

reg mrd;
integer i;

initial
begin
   for (i=0;i<=255;i= i+1)
      ram_data[i] <= 8'b00000000;
   #1;
  $readmemh("ram.rom",ram_data);
end

//always @ (loadfile)
//begin
//   if (loadfile == 1)
//       $readmemh("ram.rom",ram_data);
//end

always @ (nrawr or ncs or address or data_in)
begin
   if ({ncs,nrawr} === 2'b00)
     ram_data[address] <= data_in;
end 

assign data_out = ({ncs,nrard} === 2'b00) ? ram_data[address]:8'bzzzzzzzz;

endmodule